Chapter 5 Arithmetic Functions and Circuits J.J. Shann Arithmetic ckt: (cid:132) a combinational ckt that performs arithmetic ops w/ binary — numbers or w/ decimal numbers in a binary code E.g.: addition, subtraction, multiplication, and division (cid:190) Develop arithmetic ckts by means of hierarchical, (cid:132) iterative design J.J. Shann 5-2 Chapter Overview 5-1 Iterative Combinational Circuits 5-2 Binary Adders 5-3 Binary Subtraction 5-4 Binary Adder-Subtractors 5-5 Binary Multiplication 5-6 Other Arithmetic Functions 5-7 HDL Representations – VHDL (×) 5-8 HDL Representations – Verilog (×) 5-9 Chapter Summary J.J. Shann 5-3 5-1 Iterative Combinational Circuits Arithmetic block: (cid:132) is typically designed to operate on binary input vectors — and produce binary output vectors. The function implemented often requires that the same — subfunction be applied to each bit position. ⇒ A function block can be designed for the subfunction and then used repetitively for each bit positions of the overall arithmetic block. cell: a subfunction block (cid:132) the overall implementation is an array of cell — → iterative array J.J. Shann 5-4 Iterative array Iterative array: (cid:132) a special case of hierarchical ckts — is useful in handling vectors of bits — has the repetitive nature of the ckt & the association of a — vector index w/ each of the ckt cells. The cell in the array are often, but not always, identical. — E.g.: Block diagram of an iterative ckt — J.J. Shann 5-5 5-2 Binary Adders Half adder: add 2 bits (cid:132) Full adder: add 2 input bits and a carry-in bit (cid:132) Binary ripple carry adder: add two n-bit binary (cid:132) numbers Carry-lookahead adder (cid:132) J.J. Shann 5-6 A. Half Adder Half adder (HA): adds 2 bits (cid:132) <Design Procedure> Step 1: Specification The basic rule for binary addition: 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 1 0 Input variables: 2; augend and addend bits; X, Y Output variables: 2; sum and carry bits; S, C J.J. Shann 5-7 Step2: Formulation Step 3: Optimization S = x′y + xy′ = x ⊕ y C = xy Step 4: Technology mapping J.J. Shann 5-8 B. Full Adder Full adder (FA): add 3 bits (cid:132) <Design Procedure> Step 1 Input variables: 3; 2 significant bits X, Y & a carry-in bit Z Output variables: 2; sum and carry bits S, C Step 2 J.J. Shann 5-9 Step3 Step 4 J.J. Shann 5-10