A R E A A R R A Y I N T E R C O N N E C T I O N H A N D B O O K E D I T E D B Y K A R L J . P U T T L I T Z P A U L A . T O T T A w Springer Science+Business Media, LLC Library of Congress Cataloging-in-Publication Data The area array interconnection handbook / edited by, Karl L. Puttlitz and Paul Totta p. cm. ISBN 978-1-4613-5529-8 ISBN 978-1-4615-1389-6 (eBook) DOI 10.1007/978-1-4615-1389-6 1. Hybrid integrated circuits. 2. Microelectronics. I. Puttlitz, Karl J. II. Totta, Paul. TK7874.A73.2001 621.3815—dc21 200108653 © 2001 Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 2001 A l l rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC Printed on acid-free paper. AREA ARRAY INTERCONNECTION HANDBOOK Dedication It is with pleasure that we the editors dedicate this work to the over 80 contributors who la- bored long hours and freely shared their knowledge and expertise to create the most complete and authoritative source for die and package-level, area array microelectronic packaging and interconnection technology under one cover, which is both easy to read and understand. We particularly appreciate their patience, diligence, and dedication, without which this project could not have come to fruition. The chapter champions and major contributions are noted in bold and associate contributors in standard print for each chapter. We also dedicate this work to the contributor's families and particularly our wives Dianne and MaryAnn for their patience and understanding during the many months the manuscript was in preparation. KARL J. PUITLITZ PAUL A. TOITA Contents Foreword lxi Preface lxiii Editor Biographies Ixvii Chapter 1 History of Flip Chip and Area Array Technology 1 1.1 Introduction 1 1.2 Early Electronics 1 1.3 Solid Logic Technology-The Birth of Flip Chip Packaging 2 1.3.1 Pre-SLT Packaging 2 1.3.2 SLT Transistor Design 4 1.3.3 Die-Level Hermeticity and I/O Bumps 4 1.3.4 Flip Chip Non-Hermetic Packaging 5 1.3.5 Hybrid Integrated Circuit Technology 6 1.4 Early Ball-Connection Development 7 1.4.1 Gold Ball Terminals 7 1.4.2 Wettable Terminal Pads 7 1.4.3 Ball Collapse 7 1.4.3.1 Collapse solutions 8 1.4.3.2 Other terminal changes 8 1.5 C-4 Flip Chip Development 10 1.5.1 Thick-Film Electrode Problem with C4 10 1.5.2 Other Chip Changes in Integrated Circuits 10 1.5.3 Self-Alignment in C4 11 1.5.4 Thermal Cycle Solder-Joint Fatigue Life 12 1.5.4.1 Elongated bumps and fatigue life extension 12 1.6 Beginning of Area Array Pads on Chips 12 1.6.1 Protect Diodes 12 1.6.2 I/O Over Active Area 12 1.6.3 Substrate Thin-Film Metallization 12 1.6.4 Multilevel Thin-Film Substrate Wiring 15 1.6.5 Multilayer Ceramic Modules 15 1.6.6 Redistribution Layers 17 1.6.7 Multilayer Chip Wiring 17 1.6.8 Peripheral to Area Array Shift 17 1.7 Alternative Interconnection Techniques 17 1.7.1 Beam Leads 17 viii Contents 1.7.2 Tape Automated Bonding 18 1.7.3 Wire Bonding 19 1.8 Peripheral vs Area Array Chip Wiring 21 1.8.1 Peripheral Limitations 21 1.8.2 I/O Requirements 22 1.8.3 Peripheral vs Area Array Efficiency 22 1.9 Packaging Technology 23 1.9.1 Transfer Molded Plastic Packages and Surface Mount Assembly 23 1.9.1.1 Surface mount vs pin-in-hole assembly 23 1.9.2 Area Array Packaging 24 1.9.3 Ceramic Multichip Modules 24 1.9.3.1 High-performance capabilities 24 1.9.3.2 CTE-matching ceramic 25 1.9.3.3 State-of-the-art server packaging 26 1.9.4 Direct Chip Attach on Organics 26 1.9.4.1 Flip chip underfill materials 26 1.9.4.2 Commodity market impact 27 1.9.4.3 Plastic ball grid array package 27 1.9.4.4 Chip scale packages vs DCA 28 1.10 The Future Issues with Area Array 31 1.10.1 Widespread Availability of Low Cost, Good Flip Chips 31 1.10.2 Reliability Requirements Appropriate for the Application 31 1.10.3 The No-Pb Quandry for Electronic Packaging 31 1.10.4 Ceramic vs Organic Packaging 32 References 32 Part I Chip· Level Technology 37 Chapter 2 Wafer Bumping 39 2.1 Introduction 39 2.1.1 IBM SLT and C4 Efforts 40 2.1.2 General Motors' Early Flip Chip 40 2.1.3 Inexpensive Plastic Packages 40 2.1.4 Growing Niche for Flip Chip 40 2.1.5 Electroplated C4 Evolution 40 2.1.6 SLC and DCA 43 2.1.7 The Interconnect Paradigm Shift 43 2.1.8 MCNClUnitive Electroplated C4 43 2.1.9 Delphi-DelcolFlip Chip Technologies C4 44 2.1.10 TV BerlinlFraunhofer/Pac Tech Bumping 44 2.1.11 MicroFab Solder Jet Bumping 44 2.1.12 Non-solder Adhesive Bumping 44 2.1.13 Recent Developments 44 2.2 Evaporative Bumping 45 2.2.1 IBM Copper Ball Solderable Terminal 45 2.2.2 Solder Pre-placement Choices 45 2.2.3 Solder Evaporation 45 2.2.4 BLM Evaporation 46 2.2.5 Sputter Cleaning 47 Contents ix 2.2.5.1 Wafer contamination problem 47 2.2.5.2 Ex situ sputter cleaning 47 2.2.5.3 In situ sputter cleaning 48 2.2.5.4 Rf sputter cleaning 48 2.2.6 Cr-Cu-Au/Solder Evaporation and Reflow 48 2.2.6.1 Chromium deposition 48 2.2.6.2 Chromium-copper codeposition or "Phasing" 48 2.2.6.3 Solution-assisted spalling 48 2.2.6.4 Copper deposition 49 2.2.6.5 Au deposition 49 2.2.6.6 Solder deposition 49 2.2.6.7 Cu balling of SLT wafers 51 2.2.6.8 Reflowing solder at the wafer level 51 2.2.7 Extendibility to Larger Wafers 52 2.2.8 Modern Evaporation Tooling 52 2.2.9 Variations on the Theme 54 2.2.9.1 Evaporation through a polymer mask 54 2.2.9.2 Hitachi sputtered CrCuAu UBM 54 2.2.9.3 Tin-cap C4 54 2.2.9.4 Motorola E3 56 2.3 Electrodeposition of Solder Bumps 56 2.3.1 Introduction 56 2.3.2 Overview 56 2.3.3 History of Electrodeposited Solder Bumps 56 2.3.3.1 Philips "IC on tape" 56 2.3.3.2 Hitachi electroplate 57 2.3.3.3 APTOS copper stud 57 2.3.3.4 Unitive electronics' intermetallic etch mask 58 2.3.3.5 VTT electronics' patterned barrier-blanket seed process 58 2.3.3.6 AT&T resist-less 58 2.3.3.7 IBM's electrodeposited C4 59 2.3.3.8 AMP's silicon waferboard technology (SWT) 59 2.3.4 Process Flow Options 59 2.3.4.1 Discrete seed, copper plate, solder plate 60 2.3.4.2 Discrete seed, nickel plate, solder plate 61 2.3.4.3 Patterned barrier, blanket seed, solder plate 63 2.3.4.4 Phased seed, solder plate 63 2.3.5 Issues in Electrodeposition of Solder Bumps 63 2.3.5.1 Seed layer conductivity 63 2.3.5.2 Seed layer oxidation 64 2.3.5.3 Seed layer nucleation 64 2.3.5.4 Seed layer etching 64 2.3.5.5 Photoresist thickness 64 2.3.5.6 Photoresist patterning 64 2.3.5.7 Photoresist development 64 2.3.5.8 Electrochemical kinetics 64 2.3.5.9 Hydrogen overpotential 65 2.3.5.10 Alloy control 65 2.3.5.11 Deposition rate 65 x Contents 2.3.5.12 Deposition uniformity 66 2.3.5.13 Bath control 66 2.3.6 Conclusion 66 2.4 Flex-on-cap Bumping Technology 66 2.4.1 Introduction 66 2.4.2 Solder Paste Bumping Technology 66 2.4.2.1 In situ wafer clean 66 2.4.2.2 UBM deposition 66 2.4.2.3 UBM patterning 67 2.4.2.4 Solder paste deposition 67 2.4.2.5 Production bump pitch roadmap 67 2.4.2.6 Bump mechanical specifications 67 2.4.2.7 Bump design rules 67 2.4.2.8 Repassivation 68 2.4.2.9 Bump height distribution 68 2.4.3 Bump Structure-UBM 68 2.4.3.1 Characteristics and requirements of UBM 68 2.4.3.2 AIINiV/Cu UBM design 68 2.4.3.3 UBM compatibility with probed wafers 72 2.4.4 Bump Structure-Solder 72 2.4.4.1 Solder alloy control requirements 72 2.4.4.2 63SnlPb solder alloy 72 2.4.4.3 Low alpha particle solder 73 2.4.4.4 lOSn/Pb solder alloy 73 2.4.4.5 Lead-free solder alloys 73 2.4.5 Conclusions 76 2.5 Low-Cost Bumping Technology Based on Electroless Ni and Solder Paste 76 2.5.1 Introduction 76 2.5.1.1 Electroless plating and maskless process advantages 76 2.5.2 Electroless Ni/Au Under Bump Metallization (UBM) 77 2.5.2.1 Electroless NilA u bumping-the process steps 79 2.5.2.2 Electroless NilA u bumping---characteristics 79 2.5.2.3 Electroless NilA u bumping-wafer design rules 80 2.5.3 Solder Bumping Technology 81 2.5.3.1 Wafer level solder printing 81 2.5.3.2 Lead-free solder printing 83 2.5.3.3 Solder bumping for repair using single point solder ball placement 83 2.5.3.4 Laser scan reflow balling 84 2.5.4 Bumping for 300 mm Wafers 86 2.5.5 Conclusions 86 2.6 Solder Jet Technology for Wafer Bumping 88 2.6.1 Introduction 88 2.6.2 Background of Ink-Jet Technology 88 2.6.3 Printhead 89 2.6.4 Drop Size Modulation 89 2.6.5 Print-on-the-Fly 90 Contents xi 2.6.6 Test Vehicle Printing/Bump Metallurgy 90 2.6.7 High and No-Lead Solders 91 2.6.7.1 Bumping demonstration and assessment 92 2.6.8 Conclusions 92 2.7 Conductive Adhesive Joining and Bumping for DCA Applications 93 2.7.1 Introduction 93 2.7.2 Bumping 94 2.7.2.1 Electroplating 94 2.7.2.2 Electroless nickel bumps 95 2.7.2.3 Stud wire bumping 95 2.7.2.4 Polymer bumps 95 2.7.3 Adhesives 95 2.7.3.1 Contact mechanisms in adhesive joints 96 2.7.4 Isotropic Conductive Adhesive 96 2.7.4.1 Metal content increases elastic modulus 97 2.7.4.2 Underfill 97 2.7.5 ICA on Rigid Substrates 97 2.7.5.1 Polymer bumps 97 2.7.5.2 Plated metal bumps 98 2.7.5.3 Citizen LCD 98 2.7.5.4 Philips COG 98 2.7.6 Stud Ball Bumping (SBB) Process 98 2.7.6.1 Matsushita ICA 98 2.7.6.2 Fujitsu microprocessor 99 2.7.7 Anisotropic Conductive Adhesive 99 2.7.7.1 ACA bonding parameters 100 2.7.7.2 Criteria for a good flip chip joint 100 2.7.7.3 Softening of PCB 100 2.7.7.4 Material properties of adhesives 100 2.7.7.5 Deformation of filler particles 102 2.7.7.6 Examples of ACA 102 2.7.7.7 Solder-filled ACAs 105 2.7.7.8 Smart-card application 106 2.7.7.9 Flip chip on rigid board application 107 2.7.8 Use of Conductive Particles 107 2.7.8.1 Sharp; "ELASTIC" 107 2.7.8.2 Seiko Epson 108 2.7.8.3 Mitsubishi 109 2.7.9 Non-conductive Adhesive 109 2.7.9.1 Matsushita NCA 110 2.7.10 General Reliability and Degradation Mechanisms 111 2.7.11 Conclusions 111 Acknowledgments 111 References 112 Chapter 3 Wafer-Level Test 117 3.1 Introduction 117 3.1.1 Introduction to Test 117 3.1.2 Introduction to Probes 118 3.2 Test Strategy 118 xii Contents 3.2.1 Prime Tenet 118 3.2.2 Approach 118 3.2.2.1 Hierarchical flow 119 3.2.2.2 Design for test 119 3.2.2.3 Adoption of area-array technology 119 3.2.2.4 Fault modeling 121 3.2.2.5 Structural testing using scan techniques 121 3.3 Test Types 122 3.3.1 In-Line Tests 123 3.3.1.1 Test sites 123 3.3.1.2 Kerf structures 123 3.3.1.3 Pad layout 123 3.3.1.4 Probe constraints 124 3.3.2 Wafer Final Test 124 3.3.2.1 Wafer test ordering 124 3.3.2.2 Multiple test cycles 124 3.3.2.3 Test objectives 125 3.3.3 Wafer Probing Test Considerations 126 3.3.3.1 Product/test type 126 3.3.3.2 Physical layout 126 3.3.3.3 Die pad metallization 126 3.3.3.4 Probe types 126 3.3.3.5 Singulated die test 127 3.3.3.6 Probe interface 127 3.3.3.7 Space transformer 127 3.3.3.8 Power supply distribution 127 3.3.3.9 Remote sensing 127 3.3.3.10 Contact verification 127 3.3.3.11 Maintainability considerations 128 3.4 Product Probers and Handlers 128 3.4.1 Wafer Prober 128 3.4.1.1 Overview 128 3.4.1.2 Integral subsystem 128 3.4.1.3 Basic functions 129 3.4.2 Materials Handler 129 3.4.2.1 Wafer diameter/thickness consideration 129 3.4.2.2 Handling single wafers 130 3.4.2.3 Wafer IDs 130 3.4.2.4 Typical process flow 130 3.4.3 Alignment 130 3.4.3.1 Sophisticated systems 130 3.4.3.2 Alignment processes 130 3.4.3.3 Probe mark inspection 132 3.4.3.4 Environment control 133 3.4.3.5 Z-Drive considerations 133 3.5 Probes for Semiconductor Devices 133 3.5.1 Background 133 3.5.2 Introduction 134 3.5.3 Fundamental Requirements 135 3.5.4 Peripheral Probe Materials 136 3.5.5 Peripheral Probes 136