VITA PO Box 19658, Fountain Hills, AZ 85269 PH: 480-837-7486 Email: [email protected] URL: http://www.vita.com Approved American National Standard ANSI/VITA 46.9 PMC/XMC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Modules Standard Abstract This VITA 46 (VPX) subsidiary standard defines PMC or XMC mezzanine rear I/O pin mappings to VITA 46.0 plug-in module backplane connectors. Approved November 2010 American National Standards Institute, Inc. American Approval of an American National Standard requires verification by ANSI that the requirements for due process, consensus, and National other criteria for approval have been met by the standards developer. Standard Consensus is established when, in the judgment of the ANSI Board of Standards Review, substantial agreement has been reached by directly and materially affected interests. Substantial agreement means much more than a simple majority, but not necessarily unanimity. Consensus requires that all views and objections be considered, and that a concerted effort be made toward their resolution. The use of American National Standards is completely voluntary; their existence does not in any respect preclude anyone, whether he has approved the standards or not, from manufacturing, marketing, purchasing, or using products, processes, or procedures not conforming to the standards. The American National Standards Institute does not develop standards and will in no circumstances give an interpretation of any American National Standard. Moreover, no person shall have the right or authority to issue an interpretation of an American National Standard in the name of the American National Standard Institute. Requests for interpretations should be addressed to the secretariat or sponsor whose name appears on the title page of this standard. CAUTION NOTICE: This American National Standard may be revised or withdrawn at any time. The procedures of the American National Standards Institute require that action be taken periodically to reaffirm, revise, or withdraw this standard. Purchases of American National Standards may receive current information on all standard by calling or writing the American National Standards Institute. Published by VMEbus International Trade Association (VITA) PO Box 19658, Fountain Hills, AZ 85269 Copyright © 2010 by VMEbus International Trade Association All rights reserved. Permission of the publisher is required to reproduce this document or any part of it. Printed in the United States of America - R1.0 ISBN 1-885731-63-9 ANSI/VITA 46.9 Table of Contents 1 INTRODUCTION (NORMATIVE)...................................................................................................8 1.1 OVERVIEW.....................................................................................................................................8 1.2 OBJECTIVE...................................................................................................................................11 1.3 ORGANIZATION AND SCOPE OF THIS DOCUMENT........................................................................11 1.4 TERMINOLOGY.............................................................................................................................11 1.4.1 Normative and Informative Content......................................................................................11 1.4.2 Normative Key Words............................................................................................................12 1.4.3 Other Terms and Definitions..................................................................................................13 1.5 REFERENCES................................................................................................................................15 2 VITA-46.9 COMPLIANCE (NORMATIVE)..................................................................................17 2.1 GENERAL FUNCTIONAL CRITERIA...............................................................................................17 2.2 MEZZANINE MODULE TYPE INDICATOR......................................................................................17 2.3 BACKPLANE CONNECTOR PIN FIELD MAPPING IDENTIFIER.........................................................18 3 MEZZANINE CARD REAR I/O PATTERN MAPS (INFORMATIVE)....................................19 3.1 BASIC PATTERN MAP OPTIONS....................................................................................................19 3.2 PATTERN P64S.............................................................................................................................21 3.3 PATTERN X38S............................................................................................................................23 3.4 PATTERN X24S............................................................................................................................24 3.5 PATTERN X8D..............................................................................................................................25 3.6 PATTERN X12D............................................................................................................................27 3.7 PATTERN X8D+X12D..................................................................................................................28 3.8 PATTERN X12D+X8D..................................................................................................................30 4 3U VITA 46.0 CONNECTOR PIN MAPPING (NORMATIVE).................................................32 4.1 P64S VITA 46.0 CONNECTOR PIN FIELD.....................................................................................33 4.2 X12D+P64S BACKPLANE PIN FIELD............................................................................................34 4.3 X8D+X12D BACKPLANE PIN FIELD.............................................................................................36 4.4 X24S+X8D+X12D PIN FIELD......................................................................................................38 4.5 X38S+X8D PIN FIELD..................................................................................................................39 4.6 X12D+X38S+X8D PIN FIELD......................................................................................................41 4.7 3U CARRIER X38S+X8D+X12D VITA 46.0 CONNECTOR PIN FIELD..........................................42 5 6U VITA 46.0 CONNECTOR PIN MAPPING (NORMATIVE)..................................................45 5.1 P64S PIN FIELD............................................................................................................................47 5.2 P64S+X12D PIN FIELD................................................................................................................49 5.3 P64S+X12D+X8D PIN FIELD.......................................................................................................52 5.4 X38S+X8D+X12D PIN FIELD......................................................................................................55 5.5 X38S+X12D PIN FIELD................................................................................................................58 5.6 X38S+X12D+X8D PIN FIELD......................................................................................................61 6 ELECTRICAL SPECIFICATIONS (NORMATIVE)....................................................................65 6.1 SINGLE-ENDED I/O LAYOUT ELECTRICAL CHARACTERISTICS.....................................................65 6.2 DIFFERENTIAL I/O LAYOUT ELECTRICAL CHARACTERISTICS.....................................................66 6.3 REAR I/O SIGNAL BUFFERS.........................................................................................................67 6.4 MEZZANINE REAR I/O SIGNAL DIRECTIONALITY........................................................................67 6.4.1 Differential Pair Signal Direction Guidelines.......................................................................67 6.4.2 Single-Ended Signal Direction Guidelines............................................................................68 7 APPENDIX (INFORMATIVE)........................................................................................................69 7.1 P64SS PATTERN MAP...................................................................................................................69 Page 3 of 70 ANSI/VITA 46.9 List of Figures FIGURE 1.1-1: 3U VPX CARRIER PIN FIELD OPTIONS.....................................................................................9 FIGURE 1.1-2: 6U VPX CARRIER PIN FIELD OPTIONS...................................................................................10 FIGURE 3.2-1: P64S PATTERN MAP................................................................................................................22 FIGURE 3.3-1: X38S PATTERN MAP...............................................................................................................23 FIGURE 3.4-1: X24S PATTERN MAP...............................................................................................................25 FIGURE 3.5-1: X8D PATTERN MAP.................................................................................................................26 FIGURE 3.6-1: X12D PATTERN MAP...............................................................................................................27 FIGURE 3.7-1: X8D+X12D PATTERN MAP.....................................................................................................29 FIGURE 3.8-1: X12D+X8D PATTERN MAP.....................................................................................................30 FIGURE 4-1: 3U VPX CARRIER VITA 46.0 CONNECTOR PIN FIELD SUMMARY............................................32 FIGURE 4.1-1 3U CARRIER P64S MAPPING..............................................................................................33 FIGURE 4.2-1: 3U CARRIER X12D+P64S MAPPING........................................................................................35 FIGURE 4.3-1: 3U CARRIER X8D+X12D MAPPING........................................................................................37 FIGURE 4.4-1: 3U CARRIER X24S+X8D+X12D MAPPING.............................................................................38 FIGURE 4.5-1: 3U CARRIER X38S+X8D MAPPING.........................................................................................40 FIGURE 4.6-1: 3U CARRIER X12D+X38S+X8D MAPPING.............................................................................41 FIGURE 4.7-1: 3U CARRIER X38S+X8D+X12D MAPPING.............................................................................43 FIGURE 5-1: 6U VPX CARRIER BACKPLANE PIN FIELD SUMMARY...............................................................45 FIGURE 5.1-1: 6U CARRIER P64S MAPPING...................................................................................................47 FIGURE 5.2-1: 6U CARRIER P64S+X12D MAPPING........................................................................................50 FIGURE 5.3-1: 6U CARRIER P64S+X12D+X8D MAPPING..............................................................................53 FIGURE 5.4-1: 6U CARRIER X38S+X8D+X12D MAPPING.............................................................................56 FIGURE 5.5-1: 6U CARRIER X38S+X12D MAPPING.......................................................................................59 FIGURE 5.6-1: 6U CARRIER X38S+X12D+X8D MAPPING.............................................................................62 FIGURE 7.1-1: P64SS MAPPING PATTERN.......................................................................................................69 Page 4 of 70 ANSI/VITA 46.9 List of Tables TABLE 1.4.3-1: TERMS AND DEFINITIONS......................................................................................................13 TABLE 2.2-1: MEZZANINE TYPE LABEL.........................................................................................................17 TABLE 3.1-1: 4X SRIO BACKPLANE PORT WIRING FOR VITA 42.2 XMC....................................................20 TABLE 3.1-2: 4X SRIO BACKPLANE PORT WIRING FOR VITA 46.3 VPX SERIAL LINK................................21 TABLE 3.2-1: P64S VITA 46.0 CONNECTOR PIN FIELD TEMPLATE...............................................................22 TABLE 3.3-1: X38S VITA 46.0 CONNECTOR PIN FIELD TEMPLATE...............................................................24 TABLE 3.4-1: X24S VITA 46.0 CONNECTOR PIN FIELD TEMPLATE...............................................................25 TABLE 3.5-1: X8D VITA 46.0 CONNECTOR PIN FIELD TEMPLATE................................................................26 TABLE 3.6-1: X12D CONNECTOR PIN FIELD TEMPLATE................................................................................27 TABLE 3.7-1: X8D+X12D VITA 46.0 CONNECTOR PIN FIELD TEMPLATE.....................................................29 TABLE 3.8-1: X12D+X8D VITA 46.0 CONNECTOR PIN FIELD TEMPLATE.....................................................31 TABLE 4-1: 3U VPX MEZZANINE REAR I/O PIN FIELD SUMMARY................................................................33 TABLE 4.1-1: P2W1-P64S VITA 46.0 CONNECTOR PIN FIELD.......................................................................34 TABLE 4.2-1: P1W9P2-X12D+P64S VITA 46.0 CONNECTOR PIN FIELD.......................................................36 TABLE 4.3-1: P2W7-X8D+X12D VITA 46.0 CONNECTOR PIN FIELD............................................................37 TABLE 4.4-1: P2W1-X24S+X8D+X12D VITA 46.0 CONNECTOR PIN FIELD.................................................39 TABLE 4.5-1: P2W3-X38S+X8D VITA 46.0 CONNECTOR PIN FIELD.............................................................40 TABLE 4.6-1: P1W9P2-X12D+X38S+X8D VITA 46.0 CONNECTOR PIN FIELD.............................................42 TABLE 4.7-1: P1W13-X38S+X8D+X12D TO VPX-P12 MAPPING..................................................................44 TABLE 5-1: 6U VPX MEZZANINE REAR I/O PIN FIELD SUMMARY................................................................46 TABLE 5.1-1: P3W1-P64S VITA 46.0 CONNECTOR PIN FIELD.......................................................................48 TABLE 5.1-2: P5W1-P64S VITA 46.0 CONNECTOR PIN FIELD.......................................................................49 TABLE 5.2-1: P3W1P4-P64S+X12D VITA 46.0 CONNECTOR PIN FIELD.......................................................51 TABLE 5.2-2: P5W1P6-P64S+X12D VITA 46.0 CONNECTOR PIN FIELD.......................................................52 TABLE 5.3-1: P3W1P4-P64S+X12D+X8D VITA 46.0 CONNECTOR PIN FIELD..............................................54 TABLE 5.3-2: P5W1P6-P64S+X12D+X8D VITA 46.0 CONNECTOR PIN FIELD..............................................55 TABLE 5.4-1: P3W3P4-X38S+X8D+X12D VITA 46.0 CONNECTOR PIN FIELD.............................................57 TABLE 5.4-2: P5W3P6-X38S+X8D+X12D VITA 46.0 CONNECTOR PIN FIELD.............................................58 TABLE 5.5-1: P3W3P4-X38S+X12D VITA 46.0 CONNECTOR PIN FIELD......................................................60 TABLE 5.5-2: P5W3P6-X38S+X12D VITA 46.0 CONNECTOR PIN FIELD......................................................61 TABLE 5.6-1: P3W3P4-X38S+X12D+X8D VITA 46.0 CONNECTOR PIN FIELD.............................................63 TABLE 5.6-2: P5W3P6-X38S+X12D+X8D VITA 46.0 CONNECTOR PIN FIELD.............................................64 TABLE 7.1-1: P64SS PATTERN MAP...............................................................................................................70 Page 5 of 70 ANSI/VITA 46.9 Abstract This VITA 46 (VPX) subsidiary standard defines PMC or XMC mezzanine rear I/O pin mappings to VITA 46.0 plug-in module backplane connectors. Foreword The VITA 46 standard defines plug-in modules, backplanes, and chassis assemblies that are structured to support high-speed serial interconnect among boards in a system and to support plug-in modules with higher power loads and more effective thermal relief. These definitions are based on the IEEE 1101 Euroboard definitions and are a logical evolution of the VME board definitions. This standard augments the basic form factor and assembly definition in the VITA 46.0 standard by adding wiring definitions to extend rear I/O ports on mezzanines on a plug-in module to that module’s backplane connector(s). VITA 46.9 Working Group Members Developing a standard is often a long and tedious process. Many working group members put in a full day of work at their regular “day” job while participating in the development of a VITA standard. Much thanks are extended to the various participants of the VITA 46 working group for their time and effort put forth in the development of VITA 46.9. VITA 46.9 Draft Editors While straight forward in concept, creating VITA 46.9 was not simple in development. VITA 46.9 had four different draft editors. Each provided their own particular expertise before handing the duties off to the next draft editor when they relinquished their position usually due to a new assignment within their current company or to pursue a new opportunity with a different company. As VITA’s technical director, I would like to thank each draft editor for their work and hard effort in making VITA 46.9 a recognized American National Standard. Ken Boyette, Critia Computer, Inc. Jing Kwok, CWCEC Chris Eckert, GE Intelligent Platforms Embedded Systems With special thanks going to Jim Goldenberg, GE, the present 46.9 draft editor for his efforts in finishing the draft and bringing it to ANSI recognition. Page 6 of 70 ANSI/VITA 46.9 Comments, Corrections, or Additions Anyone wishing to provide comments, corrections and/or additions to this standard please direct them to the Technical Director [email protected] at the VITA office. VSO and Other Standards Information about other standards being developed by VSO as well as VME Product Directories, VME Handbooks, and general information about the VME market is available from the VITA office listed on the front cover. Page 7 of 70 ANSI/VITA 46.9 1 Introduction (Normative) The VITA 46 (VPX) family of standards defines plug-in modules, backplanes, and host chassis assemblies that build upon the utility of the IEEE 1101 Euroboard form factor by providing a series of high-speed fabric capable backplane connectors in lieu of the conventional pin and socket connectors. This VITA 46.9 standard defines connector and pin mappings to support rear I/O port wiring for single-width PMC and XMC mezzanine cards on 3U and 6U VPX plug-in modules. 1.1 Overview VPX plug-in modules might include IEEE 1386.1 PMC and or VITA 42 XMC mezzanine card installation sites for the addition of application-specific functions. These mezzanine modules can include single-ended and or differential pair rear access ports on carrier connectors Jn4 or Jn6. The Jn4 connector has 64 single-ended contacts, in two columns of 32. These contacts are capable of supporting interfaces ranging from dc logic to 1000BaseT Ethernet. This connector can be utilized by either a PMC or a XMC mezzanine module. The Jn6 connector comprises 20 differential pairs, 38 single-ended contacts, in six columns of 19, plus ground contacts to support high-speed differential signals and is used on XMC mezzanine modules. A 3U VPX carrier is capable of hosting one single-width PMC or XMC mezzanine module, and has the following general options for backplane pin field assignments to support rear I/O access for the mezzanine module: Page 8 of 70 ANSI/VITA 46.9 Figure 1.1-1: 3U VPX Carrier Pin Field Options Similarly, a 6U VPX carrier is capable of hosting either one or two single-width PMC or XMC mezzanine modules, and has the following general options for backplane pin field assignments to support rear I/O access for each mezzanine module: Page 9 of 70 ANSI/VITA 46.9 Figure 1.1-2: 6U VPX Carrier Pin Field Options In this standard, pin field combinations are named according to how the element pin fields are distributed on the backplane connectors. For example: P3w1-P64s+ P4w1-X12d+X8d defines the composite pin field containing: - one P64s pattern map for 64 single-ended contacts on the PMC-Jn4 connector - one X12d pattern map for differential pairs on XMC-Jn6 rows 5, 7, 9, 15, 17, and 19 - one X8d pattern map for differential pairs on XMC-Jn6 rows 1, 3, 11, and 13 - The first pattern after the hyphen, P64s, is mapped to the P3 connector starting at wafer 1, following in order the X12d pattern is mapped to the next available pins, in this case, to the P4 connector starting at wafer 1, and then on to X8d pattern mapped to the P4 connector starting at wafer 7. This example is the left-most pin field shown in Figure 1.1-2 above. Page 10 of 70