VIA Technologies Delivering Value Apollo PLE133 Chipset VT8601A North Bridge Single-Chip Socket-370 PCI North Bridge with 133 / 100 / 66 MHz Front Side Bus, Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller supporting PC133 / PC100 SDRAM for Desktop PC Systems Revision 1.82 October 22, 2001 VIA TECHNOLOGIES, INC. Copyright Notice: Copyright © 1998, 1999, 2000, 2001 VIA Technologies Incorporated. Printed in the United States. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. 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VT8601A Apollo PLE133 DDDDeeeelllliiiivvvveeeerrrriiiinnnngggg VVVVaaaalllluuuueeee REVISION HISTORY Document Release Date Revision Initials 0.92 12/9/98 Initial internal release DH 0.93 12/16/98 Updated pinouts to match engineering rev 0.5 document dated 12/1/98 DH 0.94 1/20/99 Updated pinouts to match engineering rev 0.8 document dated 12/22/98 DH 1.0 6/4/99 Added 133 MHz Support to Feature Bullets DH Updated / Fixed Pin Descriptions: Fixed description of strap options on MA2, MA8, and MA11-14; Removed Auxiliary Memory Port; Added REQ/GNT[4-7]#; Added GND & VCC3 pins to increase pin count to 510 (updated mech spec); Fixed definitions of RESET# & CRSTI# and changed CRSTI# to CPURSTD#; Removed PWRGD function from SERR#; Fixed definitions of SRAS#, SCAS#, and SWE#; Added note to PLLTST description Updated Device 0 Rx50-53, 68[4], 69, 6B[5-1], 6C[7-4], 70[3,0, 72[0], 76[7], 79[1- 0], 7A (added); Device 1 Rx41[0], 42[0] 1.1 6/23/99 Updated feature bullets & overview and fixed misc formatting problems DH Fixed REQ/GNT4# pinouts and CKE & DQM naming polarity Device 0 Bus 0 updated Rx2-3 Device ID, 69[7-6], 6D[6-5], 76[6] Device 0 Bus 0 added Rx2C-D, 2E-F, 50[1], 51[5], 53[2], removed 6E-6F Device 0 Bus 1 updated Rx0-3 Vendor & Device ID, Rx7-6[7] Removed AC timing specs 1.11 7/8/99 Fixed pin descriptions of CPURSTD# and SUSP DH 1.2 8/23/99 Fixed typo in device 0 Rx50[7] description; added comment about default state DH Fixed system freq divider settings (MA pin descriptions, Dev 0 Rx68[1-0]) 1.3 9/8/99 Fixed strap options on MA2-6 and MA13 pin descriptions DH Fixed Device 0 Rx52[7] strap option and removed (reserved) Device 0 Rx52[5] Removed “VIA Confidential” watermark 1.4 2/2/00 Added DSTN modes to intro/overview panel interface section DH Removed incorrect notes under CPU interface pin descriptions Fixed MA11 strapping and VCC3/VSUS3 pin descriptions Fixed Device 0 Bus 0 Rx50[1] and Rx51[1] defaults Fixed Electrical Specs absolute max temp ratings 1.5 10/24/00 Changed product name to Apollo PLE133; Fixed typos in pinout table DH Changed temp specs to be based on case instead of ambient; added power table Changed orientation of pin 1 in mech diagram to match part marking 1.6 11/1/00 Fixed product name on cover page; Fixed strap descriptions DH Fixed Rx50[7], Rx68[1-0], 6B[4], 6C[4], D0Bus1 Rx4[9], Graphics CR39[0] 1.7 12/1/00 Removed EDO, FP, VCM and PC66 DRAM support (no longer fully tested) DH Added VIA Cyrix III CPU to suported CPUs list and changed 686A to 686B Added PLLTST pin I/O type Fixed table formatting errors introduced as a result of Word 2000 upgrade Fixed Rx6B[4] and 6C[4]; Fixed spelling errors in Functional Description 1.71 4/26/01 Fixed various typographical and formatting errors DH 1.8 7/3/01 Updated company address; updated processors list DH Removed LVDS and direct panel drive support; removed MA3-6 straps Fixed SUSP pin description; Fixed Device 0 Rx6A; moved VGA regs intro 1.81 10/8/01 Clarified the difference between chipset name and north bridge part number DH Changed “VIA Cyrix III” to “VIA C3”; Fixed max memory to be 1.5GB Updated Device 0 Rx68[4], 69[7-6, 1], 6B[1]; Updated chip marking specs 1.82 10/22/01 Fixed strap pin definitions for MA14,12,11 & updated Rx50[7], 68[1-0] to match DH Revision 1.82 October 22, 2001 -i- Revision History Technologies, Inc. VT8601A Apollo PLE133 DDDDeeeelllliiiivvvveeeerrrriiiinnnngggg VVVVaaaalllluuuueeee TABLE OF CONTENTS REVISION HISTORY..........................................................................................................................................................................I TABLE OF CONTENTS....................................................................................................................................................................II LIST OF FIGURES...........................................................................................................................................................................IV LIST OF TABLES.............................................................................................................................................................................IV PRODUCT FEATURES.......................................................................................................................................................................1 SYSTEM OVERVIEW.........................................................................................................................................................................6 APOLLO PLE133 CORE LOGIC OVERVIEW....................................................................................................................................7 APOLLO PLE133 GRAPHICS CONTROLLER OVERVIEW................................................................................................................8 Capability Overview..................................................................................................................................................................8 System Capabilities....................................................................................................................................................................9 High Performance 64-bit 2D GUI............................................................................................................................................9 Highly Integrated RAMDACTM & Clock Synthesizer...........................................................................................................9 Full Feature High Performance 3D Engine............................................................................................................................9 Video Processor........................................................................................................................................................................10 Video Capture and DVD.........................................................................................................................................................10 Versatile Frame Buffer Interface...........................................................................................................................................10 Hi-Res and Hi-Ref Display Support......................................................................................................................................10 CRT Power Management (VESA DPMS).............................................................................................................................11 Flat Panel Monitor Interface..................................................................................................................................................11 Video Capture Interface.........................................................................................................................................................11 Complete Hardware Compatibility.......................................................................................................................................11 PINOUTS.............................................................................................................................................................................................12 PIN DESCRIPTIONS.........................................................................................................................................................................15 REGISTERS........................................................................................................................................................................................23 REGISTER OVERVIEW....................................................................................................................................................................23 REGISTER SUMMARY TABLES........................................................................................................................................................23 MISCELLANEOUS I/O......................................................................................................................................................................33 CONFIGURATION SPACE I/O..........................................................................................................................................................33 REGISTER DESCRIPTIONS...............................................................................................................................................................34 Device 0 Bus 0 Header Registers - Host Bridge....................................................................................................................34 Device 0 Bus 0 Host Bridge Registers....................................................................................................................................36 CPU Interface Control........................................................................................................................................................................36 DRAM Control..................................................................................................................................................................................39 PCI Bus Control.................................................................................................................................................................................44 GART / Graphics Aperture Control....................................................................................................................................................48 AGP Control......................................................................................................................................................................................50 Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge......................................................................................................52 Device 1 Bus 0 PCI-to-AGP Bridge Registers.......................................................................................................................54 AGP Bus Control...............................................................................................................................................................................54 Device 0 Bus 1 Header Registers - Graphics Accelerator....................................................................................................55 Device 0 Bus 1 Graphics Accelerator Registers....................................................................................................................58 Graphics Accelerator PCI Bus Master Registers.................................................................................................................................59 Capture / ZV Port Registers................................................................................................................................................................64 DVD Registers...................................................................................................................................................................................65 VGA Registers..........................................................................................................................................................................68 VGA Standard Registers - Introduction..............................................................................................................................................68 Revision 1.82 October 22, 2001 -ii- Table of Contents Technologies, Inc. VT8601A Apollo PLE133 DDDDeeeelllliiiivvvveeeerrrriiiinnnngggg VVVVaaaalllluuuueeee Attribute Controller Registers (AR)....................................................................................................................................................69 VGA Status / Enable Registers...........................................................................................................................................................69 VGA Sequencer Registers (SR)..........................................................................................................................................................70 VGA RAMDAC Registers.................................................................................................................................................................70 VGA Graphics Controller Registers (GR)..........................................................................................................................................71 VGA CRT Controller Registers (CR)................................................................................................................................................72 VGA Extended Registers........................................................................................................................................................73 VGA Extended Registers – Non-Indexed I/O Ports............................................................................................................................73 VGA Extended Registers – Sequencer Indexed..................................................................................................................................74 VGA Extended Registers – Graphics Controller Indexed...................................................................................................................84 VGA Extended Registers – CRT Controller Indexed..........................................................................................................................90 VGA Extended Registers – CRTC Shadow......................................................................................................................................104 3D Graphics Engine Registers..............................................................................................................................................105 Operational Concept.........................................................................................................................................................................105 Drawing...........................................................................................................................................................................................106 Geometry Primitives.........................................................................................................................................................................107 Synchronization................................................................................................................................................................................110 Functional Blocks.............................................................................................................................................................................110 Bus Interface....................................................................................................................................................................................110 Span Engine............................................................................................................................................................................111 Graphics Engine Core...........................................................................................................................................................112 Graphics Engine Organization..........................................................................................................................................................115 Setup Engine Registers.....................................................................................................................................................................116 Vertex Registers...............................................................................................................................................................................117 Rasterization Engine Registers.........................................................................................................................................................118 Pixel Engine Registers......................................................................................................................................................................125 Texture Engine Registers..................................................................................................................................................................131 Memory Interface Registers.............................................................................................................................................................133 Data Port Area..................................................................................................................................................................................133 FUNCTIONAL DESCRIPTIONS...................................................................................................................................................134 GRAPHICS CONTROLLER POWER MANAGEMENT......................................................................................................................134 Power Management States....................................................................................................................................................134 Power Management Clock Control.....................................................................................................................................134 Power Management Registers..............................................................................................................................................134 ELECTRICAL SPECIFICATIONS...............................................................................................................................................135 ABSOLUTE MAXIMUM RATINGS..................................................................................................................................................135 DC CHARACTERISTICS.................................................................................................................................................................135 POWER CHARACTERISTICS..........................................................................................................................................................136 AC TIMING SPECIFICATIONS.......................................................................................................................................................136 MECHANICAL SPECIFICATIONS.............................................................................................................................................137 Revision 1.82 October 22, 2001 -iii- Table of Contents Technologies, Inc. VT8601A Apollo PLE133 DDDDeeeelllliiiivvvveeeerrrriiiinnnngggg VVVVaaaalllluuuueeee LIST OF FIGURES FIGURE 1. VT8601A BALL DIAGRAM (TOP VIEW)................................................................................................................12 FIGURE 2. VT8601A PIN LIST (NUMERICAL ORDER)..........................................................................................................13 FIGURE 3. VT8601A PIN LIST (ALPHABETICAL ORDER)...................................................................................................14 FIGURE 4. GRAPHICS APERTURE ADDRESS TRANSLATION...........................................................................................48 FIGURE 5. PHYSICAL REGION DESCRIPTOR TABLE FORMAT......................................................................................60 FIGURE 6. PCI BUS MASTER ADDRESS TRANSLATION.....................................................................................................60 FIGURE 7. FRAME BUFFER PARAMETERS............................................................................................................................97 FIGURE 8. LIVE VIDEO DISPLAY PARAMETERS.................................................................................................................97 FIGURE 9. MECHANICAL SPECIFICATIONS - 510-PIN BALL GRID ARRAY PACKAGE..........................................137 LIST OF TABLES TABLE 1. VT8601A PIN DESCRIPTIONS....................................................................................................................................15 TABLE 2. REGISTER SUMMARY................................................................................................................................................23 TABLE 3. SYSTEM MEMORY MAP............................................................................................................................................39 TABLE 4. MEMORY ADDRESS MAPPING TABLE.................................................................................................................39 TABLE 5. VGA/MDA MEMORY/IO REDIRECTION................................................................................................................54 TABLE 6. SUPPORTED PCI COMMAND CODES.....................................................................................................................55 TABLE 7. INTERRUPT SOURCES AND CONTROLS..............................................................................................................57 TABLE 8. GRAPHICS CLOCK FREQUENCIES – 14.31818 MHZ REFERENCE.................................................................76 TABLE 9. DPMS SEQUENCE - HARDWARE TIMER MODE.................................................................................................87 TABLE 10. DPMS SEQUENCE - HARDWARE MODE IN SIMULTANEOUS DISPLAY MODE......................................87 TABLE 11. HARDWARE CURSOR PIXEL OPERATION........................................................................................................94 TABLE 12. PCI POWER MANAGEMENT STATES................................................................................................................134 TABLE 13. ABSOLUTE MAXIMUM RATINGS.......................................................................................................................135 TABLE 14. DC CHARACTERISTICS.........................................................................................................................................135 TABLE 15. DC CHARACTERISTICS.........................................................................................................................................136 TABLE 16. AC TIMING MIN / MAX CONDITIONS................................................................................................................136 Revision 1.82 October 22, 2001 -iv- Table of Contents Technologies, Inc. VT8601A Apollo PLE133 DDDDeeeelllliiiivvvveeeerrrriiiinnnngggg VVVVaaaalllluuuueeee VIA VT8601A Apollo PLE133 133 / 100 / 66 MHz Single-Chip Socket-370 PCI North Bridge, With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller supporting PC133 / PC100 SDRAM For Desktop PC Systems PRODUCT FEATURES •••• General − 510 BGA Package (35mm x 35mm ) − 2.5 Volt core with 3.3V CMOS I/O − Supports GTL+ I/O buffer Host interface − Supports separately powered 5.0V tolerant interface to PCI bus and Video interface − 2.5V, 0.25um, high speed / low power CMOS process − PC98 / 99 compatible using VIA VT82C686B (352-pin BGA) south bridge chip for Desktop and Mobile applications − 133 / 100 / 66 MHz CPU Front Side Bus (FSB) Operation •••• High Integration − Single chip implementation for 64-bit Slot-1 and Socket-370 CPUs, 64-bit system memory, 32-bit PCI with integrated 2D / 3D GUI accelerator − Apollo PLE133 Chipset: VT8601A system controller and VT82C686B PCI to ISA bridge − Chipset includes dual UltraDMA-100 / 66 / 33 EIDE, AC-97 link, 4 USB ports, integrated Super-I/O, hardware monitoring, keyboard / mouse interfaces, and RTC / CMOS •••• High Performance CPU Interface − Supports VIA C3 and Intel CeleronTM and Pentium IIITM processors − 133 / 100 / 66 MHz CPU Front Side Bus (FSB) − Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions − Five outstanding transactions (four In-Order Queue (IOQ) plus one input latch) − Supports WC (Write Combining) cycles − Dynamic deferred transaction support − Sleep mode support − System management interrupt, memory remap and STPCLK mechanism CPU DRAM GUI Core Internal AGP PCI Comments 133 MHz 133 MHz 100 MHz 66 MHz 33 MHz Synchronous (DRAM uses CPU clock) 133 MHz 100 MHz 100 MHz 66 MHz 33 MHz Pseudo-synchronous (DRAM uses GUI clock) 100 MHz 133 MHz 100 MHz 66 MHz 33 MHz Pseudo-synchronous (DRAM uses GUI clock) 100 MHz 100 MHz 100 MHz 66 MHz 33 MHz Synchronous (DRAM uses CPU clock) 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz Pseudo-synchronous (DRAM uses GUI clock) 66 MHz 100 MHz 100 MHz 66 MHz 33 MHz Pseudo-synchronous (DRAM uses GUI clock) 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz Synchronous (DRAM uses CPU clock) Revision 1.82 October 22, 2001 -1- Product Features Technologies, Inc. VT8601A Apollo PLE133 DDDDeeeelllliiiivvvveeeerrrriiiinnnngggg VVVVaaaalllluuuueeee •••• Internal Accelerated Graphics Port (AGP) Controller − AGP v1.0 compliant − Pipelined split-transaction long-burst transfers up to 533 MB/sec − Eight level read request queue − Four level posted-write request queue − Thirty-two level (quadwords) read data FIFO (128 bytes) − Sixteen level (quadwords) write data FIFO (64 bytes) − Intelligent request reordering for maximum AGP bus utilization − Supports Flush/Fence commands − Graphics Address Relocation Table (GART) − One level TLB structure − Sixteen entry fully associative page table − LRU replacement scheme − Independent GART lookup control for host / AGP / PCI master accesses − Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support •••• Concurrent PCI Bus Controller − PCI bus is synchronous / pseudo-synchronous to host CPU bus − 33 MHz operation on the primary PCI bus − Supports up to five PCI masters − Peer concurrency − Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time − Zero wait state PCI master and slave burst transfer rate − PCI to system memory data streaming up to 132Mbyte/sec − PCI master snoop ahead and snoop filtering − Six levels (double-words) of CPU to PCI posted write buffers − Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities − Enhanced PCI command optimization (MRL, MRM, MWI, etc.) − Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM − Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters − Supports L1/L2 write-back forward to PCI master read to minimize PCI read latency − Supports L1/L2 write-back merged with PCI master post-write to minimize DRAM utilization − Delay transaction from PCI master reading DRAM − Read caching for PCI master reading DRAM − Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks) − Symmetric arbitration between Host/PCI bus for optimized system performance − Complete steerable PCI interrupts − PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs Revision 1.82 October 22, 2001 -2- Product Features Technologies, Inc. VT8601A Apollo PLE133 DDDDeeeelllliiiivvvveeeerrrriiiinnnngggg VVVVaaaalllluuuueeee •••• Advanced High-Performance DRAM Controller − DRAM interface synchronous or pseudosynchronous with CPU FSB speed of 133 / 100 / 66 MHz − DRAM interface may be faster than CPU by 33 MHz to allow use of PC100 with 66 MHz Celeron CPU or use of PC133 with 100 MHz VIA C3 or Intel Pentium II or Pentium III CPU − DRAM interface may be slower than CPU by 33 MHz to allow use of older memory modules with a newer CPU − Concurrent CPU, AGP, and PCI access − Different DRAM timing for each bank − Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems − Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs − 6 banks DRAMs supported up to 1.5GB (256Mb DRAM technology) − Flexible row and column addresses − 64-bit data width only − 3.3V DRAM interface with 5V-tolerant inputs − Programmable I/O drive capability for MA, command, and MD signals − Two-bank interleaving for 16Mbit SDRAM support − Two-bank and four bank interleaving for 64Mbit SDRAM support − Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU − Independent SDRAM control for each bank − Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while accessing the current bank) − Four cache lines (16 quadwords) of CPU to DRAM write buffers − Four cache lines of CPU to DRAM read prefetch buffers − Read around write capability for non-stalled CPU read − Speculative DRAM read before snoop result − Burst read and write operation − x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM from CPU or from DRAM controller − BIOS shadow at 16KB increment − Decoupled and burst DRAM refresh with staggered RAS timing − CAS before RAS or self refresh Revision 1.82 October 22, 2001 -3- Product Features Technologies, Inc. VT8601A Apollo PLE133 DDDDeeeelllliiiivvvveeeerrrriiiinnnngggg VVVVaaaalllluuuueeee •••• General Graphic Capabilities − 64-bit Single Cycle 2D/3D Graphics Engine − Supports 2 to 8 Mbytes of Frame Buffer − Real Time DVD MPEG-2 and AC-3 Playback − Video Processor − I2C Serial Interface − Integrated 24-bit 230MHz True Color DAC − Extended Screen Resolutions up to 1600x1200 − Extended Text Modes 80 or 132 columns by 25/30/43/60 rows − DirectX 6 and OpenGL ICD API •••• Graphics Performance − Sustained 1M polygons/second and 100M pixels/second − 30fps DVD playback of 9.8Mbps MPEG-2 video with 30% headroom − Host Based AC-3 decode at only 8% utilization •••• High Performance rCADE3D™ Accelerator − 32 entry command queue, 32 entry data queue − 4Kbyte texture cache with over 90% hit rates − Pipelined Single Cycle Setup/Texturing/Rendering Engines − DirectDraw™ acceleration − Multiple buffering and page flipping Setup Engine − 32-bit IEEE floating point input data − Slope and vertex calculations − Back facing triangle culling − 1/16 sub-pixel positioning Rendering Engine − High performance single pass execution − Diffused and specula lighting − Gouraud and flat shading − Anti-aliasing including edge, scene, and super-sampling − OpenGL compliant blending for fog and depth-cueing − 16-bit Z-buffer − 8/16/32 bit per pixel color formats Texturing Engine − 1/2/4/8-bits per pixel compact palletized textures − 16/32-bits per pixel quality non-palletized textures − Pallet formats in ARGB 565, 1555, or 444 − Tri-linear, bi-linear, and point-sampled filtering − Mip-mapping with multiple Level-Of-Detail (LOD) calculations and perspective correction − Color keying for translucency 2D GUI Engine − 8/15/16/24/32-bits per pixel color formats − 256 Raster Operations (ROPs) − Accelerated drawing: BitBLTs, lines, polygons, fills, patterns, clipping, bit masking − Panning, scrolling, clipping, color expansion, sprites − 32x32 and 64x64 Hardware Cursor − DOS graphics and text modes Revision 1.82 October 22, 2001 -4- Product Features