ANALOG COMPUTING ARRAYS A Dissertation Presented to TheAcademicFaculty By MatthewR. Kucic In PartialFulfillment oftheRequirements fortheDegree DoctorofPhilosophyin ElectricalEngineering School ofElectrical andComputerEngineering GeorgiaInstituteofTechnology December 2004 Copyright©2004 byMatthewR. Kucic ANALOG COMPUTING ARRAYS Approvedby: Dr. Paul Hasler, Advisor Dr. Martin Brooke Asst. Professor, School ofECE Professor, School ofECE GeorgiaInstituteofTechnology GeorgiaInstituteofTechnology Dr. David Anderson Dr. Alan Doolittle Professor, School ofECE Professor, School ofECE GeorgiaInstituteofTechnology GeorgiaInstituteofTechnology Dr. PhillipAllen Dr.Brad Minch Professor, School ofECE Professor, School ofECE GeorgiaInstituteofTechnology OlinCollege DateApproved: August2004 To myadvisorPaul Haslerwho convinced meof graduatestudiesandmy wifeKellyKucic who convinced metostickwithgraduatestudies. ACKNOWLEDGEMENTS I wish to thank my colleagues in the Integrated Computational Electronics lab for their encouragement andsupport. iv TABLE OF CONTENTS ACKNOWLEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv LIST OFTABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii LIST OFFIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii CHAPTER 1 ANALOG COMPUTINGARRAYS . . . . . . . . . . . . . . . . 1 1.1 Analog ComputingArrays Benefits . . . . . . . . . . . . . . . . . . . . . 1 1.2 ACA Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 ACA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 ACA History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 CHAPTER 2 PROGRAMMABLEFILTER . . . . . . . . . . . . . . . . . . . 9 2.1 FilterConcept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 CapacitivelyCoupledCurrent Conveyor(C4) . . . . . . . . . . . . . . . . 13 2.3 Basic CircuitEquations . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 Time-DomainModeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.5 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CHAPTER 3 DIBL FOREXTENDING LINEAR RANGEOFC4 . . . . . . . 25 3.1 TheMOSFET RelationshipofChannel Current toDrain Voltage . . . . . 25 3.2 Drain-Induced Barrier Lowering(DIBL) . . . . . . . . . . . . . . . . . . 26 3.3 DIBL devicesinamplifiers . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 DifferentialVersion ofC4 WithDIBL . . . . . . . . . . . . . . . . . . . . 30 3.5 Floating-GateInput-WeightMultiplier . . . . . . . . . . . . . . . . . . . 32 CHAPTER 4 PROGRAMMINGARRAYS . . . . . . . . . . . . . . . . . . . . 36 4.1 Array ConfigurationoftheFloating-GateElements . . . . . . . . . . . . 36 4.2 Floating-gateDeviceOverview . . . . . . . . . . . . . . . . . . . . . . . 37 4.3 DeviceSelection inArrays . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.4 Floating-gateArray ProgrammingScheme . . . . . . . . . . . . . . . . . 42 v 4.5 Floating-gateProgrammingAlgorithm . . . . . . . . . . . . . . . . . . . 45 4.6 PogrammingSpeed Issues . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.7 CustomProgrammingBoard . . . . . . . . . . . . . . . . . . . . . . . . 51 4.8 ArchitectureIssues forArray and Non-Array Layout . . . . . . . . . . . . 58 CHAPTER 5 ROW-PARALLELPROGRAMMINGOFFLOATING-GATEEL- EMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 Row-parallel Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.1 SRAM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2.2 Sampleand Hold . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.2.3 On-chip MeasurementCounter . . . . . . . . . . . . . . . . . . . 69 5.3 Resolutionand MismatchIssues . . . . . . . . . . . . . . . . . . . . . . 70 5.4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.5 Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.5.1 Charge-pump Direction . . . . . . . . . . . . . . . . . . . . . . . 77 5.5.2 DicksonChargepump RectifyingElement . . . . . . . . . . . . . 78 5.5.3 IV Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.5.4 Pump Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.5.5 IncorporatingtheseintotheACA programmingstructure . . . . . 82 5.6 DAC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 CHAPTER 6 HANDLINGAND RETENTION ISSUES . . . . . . . . . . . . . 87 6.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2 Floating-gateDevice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 Howto ModifytheCharge . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.4 General HandlingIssues . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.5 Design toCompensateforLong-Term Effects . . . . . . . . . . . . . . . 94 6.6 Long TermTesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 vi CHAPTER 7 VECTOR QUANTIZER -ACASYSTEM . . . . . . . . . . . . . 98 7.1 MathematicalBasis ofVQ . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2 Floating-GateVQCircuit and Architecture . . . . . . . . . . . . . . . . . 101 7.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 CHAPTER 8 CONCLUSIONSAND FUTUREWORK . . . . . . . . . . . . . 107 8.1 Accomplishments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.2 Papers and Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.2.1 Journals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.2.2 Co-AuthorUtilityPatents . . . . . . . . . . . . . . . . . . . . . . 111 8.2.3 Conferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.2.4 Papers to besubmittedshortly . . . . . . . . . . . . . . . . . . . 112 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 vii LIST OF TABLES Table1 NormalizedweightsforfiltershowninFigure5 . . . . . . . . . . . . . . 11 viii LIST OF FIGURES Figure1 MotivationforACAs forsignalprocessing . . . . . . . . . . . . . . . . 3 Figure2 Illustrationofcomputingin floating-gatememoryarrays . . . . . . . . . 4 Figure3 This demonstrates thecomputingarray concept in visual block-diagram form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure4 Top levelrepresentation oftheprogrammableanalog filter . . . . . . . . 10 Figure5 Frequency responseofprogrammablebandpass filter . . . . . . . . . . . 11 Figure6 Frequency responseofprogrammablefilter . . . . . . . . . . . . . . . . 12 Figure7 Auto-zeroingfloating-gateamplifieranditsall-transistorcircuitequivalent 14 Figure8 C4 Short timescalebehavior . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure9 NormalizedversionofFig. 8 . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure10 C4 longtimescalebehavior . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure11 NormalizedversionofFig. 10 . . . . . . . . . . . . . . . . . . . . . . . 19 Figure12 FilterresponseofsingleC4 filter . . . . . . . . . . . . . . . . . . . . . . 20 Figure13 C4 2ndharmonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure14 Bandpass withQ-peaking . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure15 Spectrum oftheC4 voltageforasinusoidalinput . . . . . . . . . . . . . 23 Figure16 Impiricalmeasurementsofdrain current versusdrainvoltage . . . . . . . 26 Figure17 Cross sectionand energy band diagramofaMOSFET . . . . . . . . . . 27 Figure18 Measured datafroma short-channelMOSFET . . . . . . . . . . . . . . 28 Figure19 Measured dependenceofEarly voltageoneffectivechannel length . . . . 29 Figure20 AmplifierTransfercharacteristics withaDIBL pFET device . . . . . . . 30 Figure21 Circuit diagramofadifferentialversionofC4 . . . . . . . . . . . . . . . 31 Figure22 Four-quadrant weightedmultiplicationusingfloating-gatedevices. . . . . 32 Figure23 DifferentialStructurefor 4-QuadrantOperation . . . . . . . . . . . . . . 33 Figure24 pFET floating-gateelementcross-section . . . . . . . . . . . . . . . . . 37 ix Figure25 Deviceselectivityinarray . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure26 Array program access . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure27 pFET injectionefficiency . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure28 Floating-gatedeviceaccess forprograming. . . . . . . . . . . . . . . . . 44 Figure29 Flowchart ofprogrammingalgorithm . . . . . . . . . . . . . . . . . . . 45 Figure30 Demonstrationofprogrammingaccuracy . . . . . . . . . . . . . . . . . 46 Figure31 Singlefloating-gatedeviceprogramed toagivenvalue . . . . . . . . . . 47 Figure32 Plot of injection rate versus injection pulse width for different drain-to- sourcevoltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure33 Plot showingtheprogrammingoffourcurrent values . . . . . . . . . . . 51 Figure34 Block diagram ofprogrammingboard . . . . . . . . . . . . . . . . . . . 52 Figure35 Pictureofprogrammingboard . . . . . . . . . . . . . . . . . . . . . . . 53 Figure36 Programmingboard current measurementcircuit . . . . . . . . . . . . . 54 Figure37 Outputofcurrent measurementintegrator . . . . . . . . . . . . . . . . . 55 Figure38 Current measurement rangeand accuracy . . . . . . . . . . . . . . . . . 56 Figure39 Array programmingcolumnselectioncircuit . . . . . . . . . . . . . . . 58 Figure40 SampleACA blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure41 ACA program and testaccess . . . . . . . . . . . . . . . . . . . . . . . 60 Figure42 Array programmingtestmodification . . . . . . . . . . . . . . . . . . . 61 Figure43 Analogcepstrum processorchip . . . . . . . . . . . . . . . . . . . . . . 62 Figure44 On-chip row-measurementblock leveldiagram . . . . . . . . . . . . . . 64 Figure45 High-leveldiagram ofprogrammingsystem . . . . . . . . . . . . . . . . 65 Figure46 Row-parallel current measurementcircuit . . . . . . . . . . . . . . . . . 67 Figure47 ModifiedSRAM schematic . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure48 SRAM measured data . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure49 Sampleand holdinputvs. outputcharacteristic . . . . . . . . . . . . . . 70 Figure50 S&H decay overtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 x