ALM-1712 GPS Filter-LNA-Filter Front-End Module Data Sheet Description Features Avago Technologies’ ALM-1712 is a GPS front-end module  Very Low Noise Figure : 1.65 dB typ that combines a low-noise amplifi er (LNA) with GPS FBAR  Exceptional Cell/PCS-Band rejection fi lters. The LNA uses Avago Technologies’ proprietary GaAs Enhancement-mode pHEMT process to achieve high gain  Advanced GaAs E-pHEMT & FBAR Technology with very low noise fi gure and high linearity. Noise fi gure  Low external component count distribution is very tightly controlled. A CMOS-compatible  Shutdown current : < 1 uA shutdown pin is included either for turning the LNA on/off , or for current adjustment. The integrated fi lter  CMOS compatible shutdown pin (SD) utilizes an Avago Technologies’ leading-edge FBAR fi lter  ESD : > 3kV at RFin pin for exceptional rejection at Cell/PCS-Band frequencies.  1mm typical thickness The low noise fi gure and high gain, coupled with low  Adjustable bias current via single external resistor/ current consumption make it suitable for use in critical voltage low-power GPS applications or during low-battery  Useable down to 1.0V supply voltage situations.  Small package dimension: 4.5(L)x2.2(W)x1(H) mm3 Component Image  Meets MSL3, Lead-free and halogen free Surface Mount 4.5 x 2.2 x 1 mm3 12-lead MCOB Specifi cations (Typical performance @ 25°C) Gnd Vdd Gnd At 1.575GHz, Vdd = 2.7V, Idd = 8.0mA (pin 12) (pin 11) (pin 10) RF in (pin 1) Gnd (pin 9)  Gain = 12.8 dB 1712 Gnd (pin 2) RF Out (pin 8)  NF = 1.65 dB YMXXXX  IIP3 = +7 dBm, IP1dB = +3 dBm Gnd (pin 3) Gnd (pin 7)  S11 = -9 dB, S22 =-10 dB Gnd Vsd Gnd TOP VIEW (pin 4) (pin 5) (pin 6)  Cell-Band Rejection: > 95dBc  PCS-Band Rejection: > 90dBc Gnd Vdd Gnd (pin 10) (pin 11) (pin 12) Application Gnd (pin 9) RF in (pin 1)  GPS Front-end Module RF Out (pin 8) Gnd (pin 2) Gnd (pin 7) Gnd (pin 3) Attention: Observe precautions for Gnd Vsd Gnd BOTTOM VIEW (pin 6) (pin 5) (pin 4) handling electrostatic sensitive devices. For RF_IN (Pin 1): ESD Human Body Model = 3 kV All other pins: ESD Machine Model = 40 V Note: ESD Human Body Model = 250 V Package marking provides orientation and identifi cation “1712” = Product Code Refer to Avago Application Note A004R: “Y” = Year of manufacture Electrostatic Discharge, Damage and Control. “M” = Month of manufacture “XXXX” = Last 4 digit of lot number Application Circuit +Vdd = 2.7V Vbias Rbias L RFin RFout GPS LNA GPS Filter Filter Absolute Maximum Rating[1] T = 25°C A Symbol Parameter Units Absolute Max. Vdd Device Drain to Source Voltage[2] V 3.6 Idd Drain Current[2] mA 20 Pin,max CW RF Input Power (Vdd = 2.7V, Idd = 6mA) dBm 15 Pdiss Total Power Dissipation[4] mW 72 Tj Junction Temperature °C 150 TSTG Storage Temperature °C -65 to 150 Thermal Resistance[3] (Vdd = 2.7 V, Idd = 8mA), jc = 92.2 °C/W Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Assuming DC quiescent conditions. 3. Thermal resistance measured using Infra-Red measurement technique. 4. Board (module belly) temperature TB is 25°C. Derate 10.9 mW/°C for Tb > 143°C. 2 Electrical Specifi cations T = 25°C, Freq=1.575GHz, measured on demo board[1] unless otherwise specifi ed – Typical Performance[1] A Table 1. Performance at Vdd = Vsd = 2.7V, Idd = 8mA (Rbias = 8.2k Ohm) nominal operating conditions Symbol Parameter and Test Condition Units Min. Typ Max. G Gain dB 11 12.8 - NF Noise Figure dB - 1.65 2.1 IP1dB Input 1dB Compressed Power dBm - +3 - IIP3[2] Input 3rd Order Intercept Point (2-tone @ Fc +/- 2.5MHz) dBm - +7 - S11 Input Return Loss dB - -9 - S22 Output Return Loss dB - -10 - S12 Reverse Isolation dB - -22 - Cell Band Rejection Relative to 1.575GHz @ 827.5MHz dBc 81 104 - PCS Band Rejection Relative to 1.575GHz @ 1885MHz dBc 81 92.6 - IP1dB1885MHz Input 1dB gain compression interferer signal level dBm 30 at 1885MHz IP1dB890MHz Input 1dB gain compression interferer signal level dBm 30 at 890MHz Idd Supply DC current at Shutdown (SD) voltage mA - 8 15 Vsd=2.7V Ish Shutdown Current @ VSD = 0V uA - 0.5 - Table 2. Performance at Vdd = 1.8V, Vsd = 1.8V, Idd = 4mA (Rbias = 4.7kOhm) nominal operating conditions Symbol Parameter and Test Condition Units Typ G Gain dB 11.8 NF Noise Figure dB 1.8 IP1dB Input 1dB Compressed Power dBm 2.5 IIP3[2] Input 3rd Order Intercept Point (2-tone @ Fc +/- 2.5MHz) dBm 6 S11 Input Return Loss dB -9 S22 Output Return Loss dB -8.5 S12 Reverse Isolation dB -20 Cell Band Rejection Relative to 1.575GHz @ 827.5MHz dBc 100 PCS Band Rejection Relative to 1.575GHz @ 1885MHz dBc 90 Idd Supply DC current at Shutdown (SD) voltage Vsd=1.8V mA 4 Ish Shutdown Current @ VSD = 0V uA 0.5 Notes: 1. Measurements at 1.575GHz obtained using demo board described in Figures 6 and 7 2. 1.575GHz IIP3 test condition: FRF1 = 1572.5 MHz, FRF2 = 1577.5 MHz with input power of -20dBm per tone measured at the worst case side band 3 DC Pin Con-guration of 4-pin connector Pins 1, 4 = GND Pins pointing 1 2 3 4 Pin 2 = Shutdown (SD) out of the page Pin 3 = Vdd Supply Circuit Symbol Size Description L1 0402 22 nH Inductor (Taiyo Yuden HK100522NJ-T ) L2 0402 6.8 nH Inductor (Taiyo Yuden HK10056N8J-T) C1 0805 0.1 uF Capacitor (Murata GRM188R71C104KA01D) C2 0402 15 pF Capacitor (Kyocera CM05CH150AHF) C3 0402 6.8 pF Capacitor (Kyocera CM05CH6R8C50AHF) R1 0402 12 Ohm (KOA RK73B1ETTP120J) R2 0402 8.2 kOhm (KOA RK73B1ETTP822J) Figure 1. Demoboard and application circuit components table 4 Vdd (Pin 3) C1 R1 L1 C2 L2 Vdd 50-Ohms TL Filter LNA Filter 5500--OOhhmmss TTLL RFin RFout Vsd R2 Vsd (Pin 2) C3 Figure 2. Demoboard and application schematic diagram Notes  The module is fully matched at the input and output RF pins. The RFinput pin, pin1, is directly connected to a shunt inductor that is grounded. The RF output fi lter blocks DC. Best noise performance is obtained using high-Q wirewound inductors. This circuit demonstrates that low noise fi gures are obtainable with standard 0402 chip inductors.  C2 and L2 form a matching network that aff ects the frequency response and linearity of the LNA, these can be tuned to optimize gain and return loss.  L1 and R1 isolates the demoboard from external disturbances during measurement. It is not needed in actual application. Likewise, C1 and C3 mitigate the eff ect of external noise pickup on the Vdd and Vsd lines respectively. These components are not required in actual operation.  Bias control is achieved by either varying the Vsd voltage with/ without R2, or fi xing the Vsd voltage to Vdd and adjusting R2 for the desired current. 5 ALM-1712 Typical Performance Curves at 25°C 40 10 20 5 0 0 -20 PCS band -5 > 90 dBc R e n (dB) -40 Cell band -10 turn lo Gai > 95 dBc ss (d -60 -15 B) -80 Gain (dB) -20 Input RL Output RL -100 -25 -120 -30 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 Freq (GHz) Figure 3a. Typical S-Parameter Plot @ Vdd = 2.7V, Idd = 8mA. 20 10 0 0 -20 -10 R e n (dB)-40 -20 turn lo Gai-60 -30 ss (dB ) -80 Gain (dB) -40 Input RL Output RL -100 -50 1.5 1.52 1.54 1.56 1.58 1.6 1.62 1.64 Freq (GHz) Figure 3b. Passband response of typical S-Parameter Plot @ Vdd = 2.7V, Idd = 8mA 6 ALM-1712 Typical Performance Curves at 25°C 40 10 20 5 0 0 -20 -5 B) R d PCS band e Gain ( -40 C>e 9ll5 b daBncd > 85 dBc -10turn loss (d B -60 -15) -80 -20 Gain (dB) -100 Input RL -25 Output RL -120 -30 0 0.5 1 1.5 2 2.5 3 3.5 4 Freq (GHz) Figure 4a. Typical S-Parameter Plot @ Vdd = 1.8V, Idd = 4mA. 20 10 0 0 -20 -10 R dB) etu n ( -40 -20 rn Gai -60 -30 loss (d B ) Gain (dB) -80 Input RL -40 Output RL -100 -50 1.5 1.52 1.54 1.56 1.58 1.6 1.62 1.64 Freq (GHz) Figure 4b. Passband response of typical S-Parameter Plot @ Vdd = 1.8V, Idd = 4mA 7 ALM-1712 Typical Performance Curves at 25°C, R2 = 8.2k Ohm 16 14 14 12 12 Vdd=Vsd=2.7V 10 Vdd=Vsd=1.8V 10 A) A) 8 m 8 m d ( d ( 6 Id 6 Id 4 4 2 2 0 0 0 5 10 15 20 25 30 35 40 0 0.5 1 1.5 2 2.5 3 3.5 4 Rbias (kohm) Vsd (V) Figure 5. Idd vs Rbias at 25°C Figure 6. Idd vs Vsd for Vdd = 2.7V, Rbias = 8.2k Ohm 10 3.0 -40 25 8 2.5 85 B) d 6 E ( mA) GUR 2.0 dd ( 4 E FI I OIS N 1.5 2 0 1.0 0 0.5 1 1.5 2 2.5 3 3.5 4 2 4 6 8 10 12 14 16 18 Vsd (V) Idd (mA) Figure 7. Idd vs Vsd for Vdd = 1.8V, Rbias = 4.7k Ohm Figure 8. NF vs. Idd at Vdd = 2.7V 3.0 15 -40 25 14 2.5 85 B) d RE ( B) 13 U 2.0 d E FIG S21 ( 12 S OI N 1.5 -40 C 11 25 C 85 C 1.0 10 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 18 Idd (mA) Idd (mA) Figure 9. NF vs Idd at Vdd = 1.8V Figure 10. Gain vs. Idd at Vdd = 2.7V 8 ALM-1712 Typical Performance Curves at 25°C, R2 = 8.2k Ohm 15 110 14 105 Bc) d 13 N ( 100 O B) CTI S21 (d 12 D REJE 95 N 11 A 90 B -40 C LL -40 C E 10 25 C C 85 25 C 85 C 85 C 9 80 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 18 Idd (mA) Idd (mA) Figure 11. Gain vs. Idd at Vdd = 1.8V Figure 12. Cell band rejection vs. Idd at Vdd = 2.7V 115 94 110 92 dBc)105 dBc) 90 N ( N ( O O TI100 TI 88 C C E E REJ 95 REJ 86 D D N N BA 90 BA 84 L -40 C S -40 C L C CE 85 25 C P 82 25 C 85 C 85 C 80 80 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 18 Idd (mA) Idd (mA) Figure 13. Cell band rejection vs. Idd at Vdd = 1.8V Figure 14. PCS band rejection vs. Idd at Vdd = 2.7V 94 8 92 3 mA 6 4 mA Bc) 90 d 6 mA N ( 8 mA EJECTIO 8868 B (dBm)4 1102 mmAA AND R 84 IP1d2 S B -40 C PC 82 25 C 0 85 C 80 -2 2 4 6 8 10 12 14 16 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Idd (mA) Vdd (V) Figure 15. PCS band rejection vs. Idd at Vdd = 1.8V Figure 16. IP1dB vs. Vdd at 25°C 9 ALM-1712 Typical Performance Curves at 25°C, R2 = 8.2k Ohm 12 10 12 mA 10 mA 8 8 mA m) dB 6 6 mA 3 ( P II 4 4 mA 3 mA 2 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 Vdd (V) Figure 17. IIP3 vs. Vdd at 25°C Figure 18. Edwards-Sinsky Output Stability Factor (Mu) at Vdd = 2.7V Figure 19. Edwards-Sinsky Input Stability Factor (Mu) at Vdd = 2.7V Figure 20. Edwards-Sinsky Output Stability Factor (Mu) at Vdd = 1.8V Figure 21. Edwards-Sinsky Input Stability Factor (Mu) at Vdd = 1.8V 10