(cid:2)(cid:17)(cid:14)(cid:14)(cid:20)(cid:2)(cid:14)(cid:13)(cid:18)(cid:12) (cid:4)(cid:14)(cid:13)(cid:8)(cid:17)(cid:7)(cid:16)(cid:15) (cid:10)(cid:14)(cid:13)(cid:11) (cid:5)(cid:9)(cid:19)(cid:6)(cid:15) (cid:3)(cid:12)(cid:15)(cid:16)(cid:14)(cid:17)(cid:11)(cid:9)(cid:12)(cid:16)(cid:15) ADS8484 SLAS511–NOVEMBER2007 18-BIT, 1.25-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE FEATURES • 48-Pin7x7QFNPackage 1 • 1.25-MHzSampleRate APPLICATIONS • ±1.5LSBTyp,±2.5LSBMaxINL • Medical Instruments • +0.8/-0.6LSBTyp,+1.5/-1LSBMaxDNL • OpticalNetworking • 18-BitNMCEnsuredOverTemperature • TransducerInterface • ±0.5-mVOffsetError • HighAccuracyDataAcquisitionSystems • ±0.05-PPM/(cid:176) COffsetErrorDrift • Magnetometers • ±0.1%FSRGainError • ±0.5-PPM/(cid:176) CGainError Drift DESCRIPTION • 98.5dB SNR,–120dbTHD,121dBSFDR The ADS8484 is an 18-bit, 1.25-MSPS A/C converter • ZeroLatency with an internal 4.096-V reference and a • LowPower: 235mWTypat1.25MSPS pseudo-bipolar, fully differential input. The device includes a 18-bit capacitor-based SAR A/D converter • Pseudo-Bipolar FullyDifferentialInputRange: with inherent sample and hold. The ADS8484 offers a Vrefto–Vref full 18-bit interface, a 16-bit option where data is read • OnboardReferencewith6PPM/(cid:176) CDrift using two read cycles, or an 8-bit bus option using • OnboardReferenceBuffer threereadcycles. • High-SpeedParallelInterface The ADS8484 is available in a 48-lead 7x7 QFN package and is characterized over the industrial • WideDigitalSupply2.7V to5.25V –40(cid:176) Cto 85(cid:176) Ctemperaturerange. • 8-/16-/18-BitBusTransfer HIGHSPEEDSARCONVERTERFAMILY TYPE/SPEED 500kHz ~600kHz 750kHz 1MHz 1.25MHz 2MHz 3MHz 4MHz ADS8383 ADS8381 ADS8481 18-BitPseudo-Diff ADS8380(s) 18-BitPseudo-Bipolar,FullyDiff ADS8382(s) ADS8482 ADS8484 ADS8327 ADS8370(s) ADS8371 ADS8471 ADS8401 ADS8411 16-BitPseudo-Diff ADS8328 ADS8472(s) ADS8405 ADS8410(s) ADS8472 ADS8402 ADS8412 ADS8422 16-BitPseudo-Bipolar,FullyDiff ADS8406 ADS8413(s) 14-BitPseudo-Diff ADS7890(s) ADS7891 12-BitPseudo-Diff ADS7886 ADS7881 SAR Output BYTE Latches 16-/8-Bit and Parallel DATA +IN + 3-State Output Bus _ CDAC Drivers BUS 18/16 −IN Comparator REFIN Conversion CONVST REFOUT I4n.t0e9rn6a-Vl Clock Contraonl dLogic CBRUSDSY Reference 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters. ADS8484 www.ti.com SLAS511–NOVEMBER2007 Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION(1) MAXIMUM MAXIMUM NOMISSINGCODES TRANSPORT INTEGRAL DIFFERENTIAL PACKAGE PACKAGE TEMPERATURE ORDERING MODEL RESOLUTION MEDIA LINEARITY LINEARITY TYPE DESIGNATOR RANGE INFORMATION (BIT) QTY. (LSB) (LSB) Tapeandreel ADS8484IRGZT ADS8484I ±4 –1to+2 18 7x748Pin RGZ -40(cid:176)Cto85(cid:176)C 250 QFN Tapeandreel ADS8484IRGZR 1000 Tapeandreel ADS8484IBRGZT ADS8484IB ±2.5 –1to+1.5 18 7x748Pin RGZ -40(cid:176)Cto85(cid:176)C 250 QFN Tapeandreel ADS8484IBRGZR 1000 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT +INtoAGND –0.4to+VA+0.1 V –INtoAGND –0.4to+VA+0.1 V Voltage +VAtoAGND –0.3to7 V +VBDtoBDGND –0.3to7 V +VAto+VBD –0.3to2.55 V DigitalinputvoltagetoBDGND –0.3to+VBD+0.3 V DigitaloutputvoltagetoBDGND –0.3to+VBD+0.3 V T Operatingfree-airtemperaturerange –40to85 (cid:176) C A T Storagetemperaturerange –65to150 (cid:176) C stg Junctiontemperature(T max) 150 (cid:176) C J Powerdissipation (TMax–T )/q J A JA QFNpackage q thermalimpedance 22 (cid:176) C/W JA Vaporphase(60sec) 215 (cid:176) C Leadtemperature,soldering Infrared(15sec) 220 (cid:176) C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 2 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8484 ADS8484 www.ti.com SLAS511–NOVEMBER2007 SPECIFICATIONS T =–40(cid:176) Cto85(cid:176) C,+VA=5V,+VBD=3Vor5V,V =4.096V,f =1.25MSPS(unlessotherwisenoted) A ref SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ANALOGINPUT Full-scaleinputvoltage(1) +IN–(–IN) –Vref Vref V +IN –0.2 Vref+0.2 Absoluteinputvoltage V –IN –0.2 Vref+0.2 Common-modeinputrange (Vref)/2–0.2 (Vref)/2 (Vref)/2+0.2 V Inputcapacitance 65 pF Inputleakagecurrent 1 nA SYSTEMPERFORMANCE Resolution 18 Bits ADS8484I 18 Nomissingcodes Bits ADS8484IB 18 INL Integrallinearity(2) AADDSS88448844IIB –2–.45 ±±11..55 2.45 (18LSbiBt)(3) ADS8484I –1 –0.6/0.8 2 LSB DNL Differentiallinearity ADS8484IB –1 –0.6/0.8 1.5 (18bit) ADS8484I –2 ±1 2 Offseterror(4) mV ADS8484IB –0.5 ±0.1 0.5 ADS8484I ±0.05 Offseterrortemperaturedrift ppm/(cid:176)C ADS8484IB ±0.05 EG Gainerror(4)(5) ADS8484I Vref=4.096V –0.1 ±0.035 0.1 %FS ADS8484IB Vref=4.096V –0.1 ±0.035 0.1 %FS ADS8484I ±0.5 Gainerrortemperaturedrift ppm/(cid:176)C ADS8484IB ±0.5 Atdc(±0.2VaroundVref/2) 60 CMRR Common-moderejectionratio dB +IN–(–IN)=1Vppat1.25MHz 55 Noise 30 m VRMS Powersupplyrejectionratio At1FFFFhoutputcode 60 dB SAMPLINGDYNAMICS Conversiontime 575 610 ns Acquisitiontime 175 200 ns Throughputrate 1.25 MHz Aperturedelay 4 ns Aperturejitter 5 ps Stepresponse 150 ns Overvoltagerecovery 150 ns (1) Idealinputspan,doesnotincludegainoroffseterror. (2) ThisisendpointINL,notbestfit. (3) LSBmeansleastsignificantbit (4) Measuredrelativetoanidealfull-scaleinput[+IN–(–IN)]of8.192V (5) Thisspecificationdoesnotincludetheinternalreferencevoltageerroranddrift. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS8484 ADS8484 www.ti.com SLAS511–NOVEMBER2007 SPECIFICATIONS (Continued) T =–40(cid:176) Cto85(cid:176) C,+VA=5V,+VBD=3Vor5V,V =4.096V,f =1.25MSPS(unlessotherwisenoted) A ref SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DYNAMICCHARACTERISTICS ADS8484I –115 VIN=8Vppat2kHz ADS8484IB –120 ADS8484I –105 THD Totalharmonicdistortion(1) VIN=8Vppat20kHz dB ADS8484IB –110 ADS8484I –100 VIN=8Vppat100kHz ADS8484IB –103 ADS8484I 96 97 VIN=8Vppat2kHz ADS8484IB 97 98.5 ADS8484I 96 SNR Signal-to-noiseratio(1) VIN=8Vppat20kHz dB ADS8484IB 98 ADS8484I 95 VIN=8Vppat100kHz ADS8484IB 97 ADS8484I 96 96 VIN=8Vppat2kHz ADS8484IB 97 98.5 ADS8484I 95 SINAD Signal-to-noise+distortion(1) VIN=8Vppat20kHz dB ADS8484IB 97 ADS8484I 93 VIN=8Vppat100kHz ADS8484IB 95 ADS8484I 117 VIN=8Vppat2kHz ADS8484IB 121 ADS8484I 107 SFDR Spuriousfreedynamicrange(1) VIN=8Vppat20kHz dB ADS8484IB 113 ADS8484I 102 VIN=8Vppat100kHz ADS8484IB 105 –3dBSmallsignalbandwidth 15 MHz (1) Calculatedonthefirstnineharmonicsoftheinputfrequency. 4 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8484 ADS8484 www.ti.com SLAS511–NOVEMBER2007 SPECIFICATIONS (Continued) T =–40(cid:176) Cto85(cid:176) C,+VA=5V,+VBD=3Vor5V,V =4.096V,f =1.25MSPS(unlessotherwisenoted) A ref SAMPLE PARAMETER TESTCONDITIONS MIN TYP MAX UNIT VOLTAGEREFERENCEINPUT Vref ReferencevoltageatREFIN 3.0 4.096 +VA–0.8 V Referenceresistance(1) 500 kΩ Referencecurrentdrain fs=1.25MHz 1 mA INTERNALREFERENCEOUTPUT Internalreferencestart-uptime From95%(+VA),with1-m F 120 ms storagecapacitor Vref Referencevoltagerange IO=0 4.081 4.096 4.111 V Sourcecurrent Staticload 10 m A Lineregulation +VA=4.75V~5.25V 60 m V Drift IO=0 ±6 PPM/(cid:176)C DIGITALINPUT/OUTPUT Logicfamily–CMOS VIH High-levelinputvoltage IIH=5m A +VBD–1 +VBD+0.3 VIL Low-levelinputvoltage IIL=5m A –0.3 0.8 V VOH High-leveloutputvoltage IOH=2TTLloads +VBD–0.6 VOL Low-leveloutputvoltage IOL=2TTLloads 0.4 Dataformat–Two'sComplement POWERSUPPLYREQUIREMENTS +VBD 2.7 3.3 5.25 V Powersupplyvoltage +VA 4.75 5 5.25 V Supplycurrent(2) fs=1.25MHz 47 52 mA Powerdissipation(2) fs=1.25MHz 235 260 mW TEMPERATURERANGE Operatingfree-air –40 85 (cid:176)C (1) Canvary±20% (2) Thisincludesonly+VAcurrent.+VBDcurrentistypical1mAwith5-pFloadcapacitanceonalloutputpins. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS8484 ADS8484 www.ti.com SLAS511–NOVEMBER2007 TIMING CHARACTERISTICS Allspecificationstypicalat–40(cid:176) Cto85(cid:176) C,+VA=+VBD=5V (1) (2) (3) PARAMETER MIN TYP MAX UNIT t Conversiontime 610 ns (CONV) t Acquisitiontime 175 ns (ACQ) t Samplecapacitorholdtime 15 ns (HOLD) t CONVSTlowtoBUSYhigh 40 ns pd1 t Propagationdelaytime,endofconversiontoBUSYlow 15 ns pd2 t Propagationdelaytime,startofconvertstatetorisingedgeofBUSY 25 ns pd3 t Pulseduration,CONVSTlow 40 ns w1 t Setuptime,CSlowtoCONVSTlow 20 ns su1 t Pulseduration,CONVSThigh 20 ns w2 CONVSTfallingedgejitter 10 ps t Pulseduration,BUSYsignallow t min ns w3 (ACQ) t Pulseduration,BUSYsignalhigh 610 ns w4 t Holdtime,firstdatabustransition(RDlow,orCSlowforreadcycle,orBYTEor h1 40 ns BUS18/16inputchanges)afterCONVSTlow t Delaytime,CSlowtoRDlow 0 ns d1 t Setuptime,RDhightoCShigh 0 ns su2 t Pulseduration,RDlow 50 ns w5 t Enabletime,RDlow(orCSlowforreadcycle)todatavalid 20 ns en t Delaytime,dataholdfromRDhigh 5 ns d2 t Delaytime,BUS18/16orBYTErisingedgeorfallingedgetodatavalid 10 20 ns d3 t Pulseduration,RDhigh 20 ns w6 t Pulseduration,CShigh 20 ns w7 t Holdtime,lastRD(orCSforreadcycle)risingedgetoCONVSTfallingedge 50 ns h2 t Propagationdelaytime,BUSYfallingedgetonextRD(orCSforreadcycle)falling pd4 0 ns edge t Delaytime,BYTEedgetoBUS18/16edgeskew 0 ns d4 t Setuptime,BYTEorBUS18/16transitiontoRDfallingedge 10 ns su3 t Holdtime,BYTEorBUS18/16transitiontoRDfallingedge 10 ns h3 t Disabletime,RDhigh(CShighforreadcycle)to3-stateddatabus 20 ns dis t Delaytime,BUSYlowtoMSBdatavaliddelay 0 ns d5 t Delaytime,CSrisingedgetoBUSYfallingedge 50 ns d6 t Delaytime,BUSYfallingedgetoCSrisingedge 50 ns d7 t BYTEtransitionsetuptime,fromBYTEtransitiontonextBYTEtransition,orBUS18/16 su5 50 ns transitionsetuptime,fromBUS18/16tonextBUS18/16. t SetuptimefromthefallingedgeofCONVST(usedtostartthevalidconversion)tothe su(ABORT) nextfallingedgeofCONVST(whenCS=0andCONVSTareusedtoabort)ortothe 60 480 ns nextfallingedgeofCS(whenCSisusedtoabort). (1) Allinputsignalsarespecifiedwitht =t =5ns(10%to90%of+VBD)andtimedfromavoltagelevelof(V +V )/2. r f IL IH (2) Seetimingdiagrams. (3) Alltimingaremeasuredwith20-pFequivalentloadsonalldatabitsandBUSYpins. 6 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8484 ADS8484 www.ti.com SLAS511–NOVEMBER2007 TIMING CHARACTERISTICS Allspecificationstypicalat–40(cid:176) Cto85(cid:176) C,+VA=5V+VBD=3V (1) (2) (3) PARAMETER MIN TYP MAX UNIT t Conversiontime 610 ns (CONV) t Acquisitiontime 175 ns (ACQ) t Samplecapacitorholdtime 15 ns (HOLD) t CONVSTlowtoBUSYhigh 40 ns pd1 t Propagationdelaytime,endofconversiontoBUSYlow 15 ns pd2 t Propagationdelaytime,startofconvertstatetorisingedgeofBUSY 25 ns pd3 t Pulseduration,CONVSTlow 40 ns w1 t Setuptime,CSlowtoCONVSTlow 20 ns su1 t Pulseduration,CONVSThigh 20 ns w2 CONVSTfallingedgejitter 10 ps t Pulseduration,BUSYsignallow t min ns w3 (ACQ) t Pulseduration,BUSYsignalhigh 610 ns w4 t Holdtime,firstdatabustransition(RDlow,orCSlowforreadcycle,orBYTEor h1 40 ns BUS18/16inputchanges)afterCONVSTlow t Delaytime,CSlowtoRDlow 0 ns d1 t Setuptime,RDhightoCShigh 0 ns su2 t Pulseduration,RDlow 50 ns w5 t Enabletime,RDlow(orCSlowforreadcycle)todatavalid 30 ns en t Delaytime,dataholdfromRDhigh 5 ns d2 t Delaytime,BUS18/16orBYTErisingedgeorfallingedgetodatavalid 10 30 ns d3 t Pulseduration,RDhigh 20 ns w6 t Pulseduration,CShigh 20 ns w7 t Holdtime,lastRD(orCSforreadcycle)risingedgetoCONVSTfallingedge 50 ns h2 t Propagationdelaytime,BUSYfallingedgetonextRD(orCSforreadcycle)falling pd4 0 ns edge t Delaytime,BYTEedgetoBUS18/16edgeskew 0 ns d4 t Setuptime,BYTEorBUS18/16transitiontoRDfallingedge 10 ns su3 t Holdtime,BYTEorBUS18/16transitiontoRDfallingedge 10 ns h3 t Disabletime,RDhigh(CShighforreadcycle)to3-stateddatabus 30 ns dis t Delaytime,BUSYlowtoMSBdatavaliddelay 0 ns d5 t Delaytime,CSrisingedgetoBUSYfallingedge 50 ns d6 t Delaytime,BUSYfallingedgetoCSrisingedge 50 ns d7 t BYTEtransitionsetuptime,fromBYTEtransitiontonextBYTEtransition,orBUS18/16 su5 50 ns transitionsetuptime,fromBUS18/16tonextBUS18/16. t SetuptimefromthefallingedgeofCONVST(usedtostartthevalidconversion)tothe su(ABORT) nextfallingedgeofCONVST(whenCS=0andCONVSTareusedtoabort)ortothe 70 480 ns nextfallingedgeofCS(whenCSisusedtoabort). (1) Allinputsignalsarespecifiedwitht =t =5ns(10%to90%of+VBD)andtimedfromavoltagelevelof(V +V )/2. r f IL IH (2) Seetimingdiagrams. (3) Alltimingaremeasuredwith20-pFequivalentloadsonalldatabitsandBUSYpins. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS8484 ADS8484 www.ti.com SLAS511–NOVEMBER2007 PIN ASSIGNMENTS RGZ PACKAGE (TOP VIEW) D Y N S0 1 23 4 5 6789G UB B BB B B BBBBD BD D DD D D DDDDB 48 4746 4544 4342 4140 393837 +VBD 1 36 +VBD BUS18/16 2 35 DB10 BYTE 3 34 DB11 CONVST 4 33 DB12 RD 5 32 DB13 CS 6 31 DB14 +VA 7 30 DB15 AGND 8 29 DB16 AGND 9 28 DB17 +VA 10 27 AGND REFM 11 26 AGND REFM 12 25 +VA 13 14 151617 18 1920 21 222324 N T CA D N N D A A DD EFI OU N+V GN +I −I GN +V +V GNGN R F A A AA E R NC − No internal connection NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. TERMINALFUNCTIONS NAME NO I/O DESCRIPTION 8,9,17,20, AGND 23,24,26, – Analogground 27 BDGND 37 – Digitalgroundforbusinterfacedigitalsupply BUSY 48 O Statusoutput.Highwhenaconversionisinprogress. Bussizeselectinput.Usedforselecting18-bitor16-bitwidebustransfer. 0:Databitsoutputonthe18-bitdatabuspinsDB[17:0]. BUS18/16 2 I 1:LasttwodatabitsD[1:0]from18-bitwidebusoutputon: a)thelowbytepinsDB[9:2]ifBYTE=0 b)thehighbytepinsDB[17:10]ifBYTE=1 Byteselectinput.Usedfor8-bitbusreading. BYTE 3 I 0:Nofoldback 1:LowbyteD[9:2]ofthe16mostsignificantbitsisfoldedbacktohighbyteofthe16mostsignificantpinsDB[17:10]. CONVST 4 I Convertstart.Thefallingedgeofthisinputendstheacquisitionperiodandstartstheholdperiod. CS 6 I Chipselect.Thefallingedgeofthisinputstartstheacquisitionperiod. 8-BITBUS 16-BITBUS 18-BITBUS DataBus BYTE=0 BYTE=1 BYTE=1 BYTE=0 BYTE=0 BYTE=0 BUS18/16=0 BUS18/16=0 BUS18/16=1 BUS18/16=0 BUS18/16=1 BUS18/16=0 DB17 28 O D17(MSB) D9 Allones D17(MSB) Allones D17(MSB) DB16 29 O D16 D8 Allones D16 Allones D16 DB15 30 O D15 D7 Allones D15 Allones D15 DB14 31 O D14 D6 Allones D14 Allones D14 DB13 32 O D13 D5 Allones D13 Allones D13 DB12 33 O D12 D4 Allones D12 Allones D12 DB11 34 O D11 D3 D1 D11 Allones D11 DB10 35 O D10 D2 D0(LSB) D10 Allones D10 8 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8484 ADS8484 www.ti.com SLAS511–NOVEMBER2007 TERMINALFUNCTIONS(continued) NAME NO I/O DESCRIPTION DB9 38 O D9 Allones Allones D9 Allones D9 DB8 39 O D8 Allones Allones D8 Allones D8 DB7 40 O D7 Allones Allones D7 Allones D7 DB6 41 O D6 Allones Allones D6 Allones D6 DB5 42 O D5 Allones Allones D5 Allones D5 DB4 43 O D4 Allones Allones D4 Allones D4 DB3 44 O D3 Allones Allones D3 D1 D3 DB2 45 O D2 Allones Allones D2 D0(LSB) D2 DB1 46 O D1 Allones Allones D1 Allones D1 DB0 47 O D0(LSB) Allones Allones D0(LSB) Allones D0(LSB) –IN 19 I Invertinginputchannel +IN 18 I Noninvertinginputchannel NC 15 Noconnection REFIN 13 I Referenceinput REFOUT 14 O Referenceoutput.Add1-m FcapacitorbetweentheREFOUTpinandREFMpinwheninternalreferenceisused. REFM 11,12 I Referenceground Synchronizationpulsefortheparalleloutput.WhenCSislow,thisservesasoutputenableandputstheprevious RD 5 I conversionresultsonthebus. 7,10,16, +VA – Analogpowersupplies,5-VDC 21,22,25 +VBD 1,36 – Digitalpowersupplyforbus TYPICAL CHARACTERISTICS INTERNALREFERENCEVOLTAGE INTERNALREFERENCEVOLTAGE DCHISTOGRAM vs vs (8192ConversionOutputs) FREE-AIRTEMPERATURE SUPPLYVOLTAGE 4000 4.098 4.0972 +VA= 5 V, 3615 +VA= 5 V, TA= 25°C 3500 +VBD = 5 V, +VBD = 5 V 4.09719 T = 25°C, 4.0975 A Frequency 223050000000 fVI n=rpe fu1=t. 2 =45 . M0M9idS6sP Vc1Sa,4,l7e4 2383 nce Voltage - V 44.0.099675 nce Voltage - V 444...000999777111678 11050000 Refere 4.096 Refere 4.09715 500 481 4.0955 4.09714 0 6 196 36 1 0 0 4.095 4.09713 -4 -3 -2 -1 0 1 2 3 4 5 -40 -25 -10 5 20 35 50 65 80 4.75 4.85 4.95 5.05 5.15 5.25 Output Code TA- Free-Air Temperature - °C Supply Voltage - V Figure1. Figure2. Figure3. Copyright©2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS8484 ADS8484 www.ti.com SLAS511–NOVEMBER2007 TYPICAL CHARACTERISTICS (continued) SUPPLYCURRENT SUPPLYCURRENT SUPPLYCURRENT vs vs vs FREE-AIRTEMPERATURE SUPPLYVOLTAGE SAMPLERATE 48 47.6 47 Supply Current - mA 444677...826 ++fViVVr=eAB f1=D=. 2 4=55. 0 V5M9 ,V6S ,PVS, Supply Current - mA 44444556674.....626482 TfViAr=e f=1= .2 2455.°0 CM9,6S PVS, Supply Current - mA 444444123456 T++VVVAreABf==D =2 45=5.° 0VC59 ,,V6 ,V 46.4 44.8 44.4 40 46 44 39 -40 -25 -10 5 20 35 50 65 80 4.75 4.85 4.95 5.05 5.15 5.25 250 500 750 1000 1250 TA- Free-Air Temperature -°C Supply Voltage - V Sample Rate - KSPS Figure4. Figure5. Figure6. DIFFERENTIALNONLINEARITY INTEGRALNONLINEARITY DIFFERENTIALNONLINEARITY vs vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE SUPPLYVOLTAGE 1.5 2.5 1.5 +VA= 5 V, T = 25°C, +VBD = 5 V, 2 A 1 fVir=e f1=. 245.0 M96S PVS, Max 1.5 Max 1 fVir=e f1=. 245.0 M96S PVS, Max 1 DNL- LSBs 0.05 INL- LSBs -00..550 ++fVV=AB 1D=.2 =55 V5M ,VS,PS, DNL- LSBs 0.05 i Min -1 Min Vref= 4.096 V Min -0.5 -1.5 -0.5 -2 -1 -1 -2.5 -40 -25 -10 5 20 35 50 65 80 -40 -25 -10 5 20 35 50 65 80 4.75 4.85 4.95 5.05 5.15 5.25 TA- Free-Air Temperature -°C TA- Free-Air Temperature -°C Supply Voltage - V Figure7. Figure8. Figure9. INTEGRALNONLINEARITY DIFFERENTIALNONLINEARITY INTEGRALNONLINEARITY vs vs vs SUPPLYVOLTAGE REFERENCEVOLTAGE REFERENCEVOLTAGE 2.5 1.5 2.5 2 VDD= 5 V, 2 VDD= 5 V, 1.5 Max 1 TfiA= =1 .2255° CM,SPS 1.5 TfiA= =1 .2255° CM,SPS Max Max 1 1 INL- LSBs-00..550 TfViAr=e f=1= .2 2455.°0 CM9,6S PVS, DNL- LSBs 0.50 INL- LSBs-00..055 -1 Min Min -1 Min -1.5 -0.5 -1.5 -2 -2 -2.5 -1 -2.5 4.75 4.85 4.95 5.05 5.15 5.25 3 3.2 3.4 3.6 3.8 4 4.2 3 3.2 3.4 3.6 3.8 4 4.2 Supply Voltage - V Reference Voltage - V Reference Voltage - V Figure10. Figure11. Figure12. 10 SubmitDocumentationFeedback Copyright©2007,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8484