16-Bit, 2 MSPS/1 MSPS, Precision, Pseudo Differential, SAR ADCs Data Sheet AD4000/AD4004 FEATURES GENERAL DESCRIPTION Throughput: 2 MSPS/1 MSPS options The AD4000/AD4004 are low noise, low power, high speed, 16-bit, INL: ±1.0 LSB maximum precision successive approximation register (SAR) analog-to-digital Guaranteed 16-bit, no missing codes converters (ADCs). The AD4000 offers a 2 MSPS throughput, and Low power the AD4004 offers a 1 MSPS throughput. They incorporate ease of 9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS (VDD only) use features that lower the signal chain power, reduce signal chain 70 µW at 10 kSPS, 14 mW at 2 MSPS (total) complexity, and enable higher channel density. The high-Z mode, SNR: 93 dB typical at 1 kHz, V = 5 V; 90 dB typical at 100 kHz REF coupled with a long acquisition phase, eliminates the need for a THD: −115 dB typical at 1 kHz, V = 5 V; −95 dB typical at 100 kHz REF dedicated high power, high speed ADC driver, thus broadening the Ease of use features reduce system power and complexity range of low power precision amplifiers that can drive these ADCs Input overvoltage clamp circuit directly while still achieving optimum performance. The input Reduced nonlinear input charge kickback span compression feature enables the ADC driver amplifier and the High-Z mode ADC to operate off common supply rails without the need for a Long acquisition phase negative supply while preserving the full ADC code range. The Input span compression low serial peripheral interface (SPI) clock rate requirement reduces Fast conversion time allows low SPI clock rates the digital input/output power consumption, broadens processor SPI-programmable modes, read/write capability, status word options, and simplifies the task of sending data across digital Pseudo differential (single-ended) analog input range isolation. 0 V to V with V from 2.4 V to 5.1 V REF REF Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface Operating from a 1.8 V supply, the AD4000/AD4004 sample an SAR architecture: no latency/pipeline delay, valid first conversion analog input (IN+) from 0 V to VREF with respect to a ground sense First accurate conversion (IN−) with VREF ranging from 2.4 V to 5.1 V. The AD4000 Guaranteed operation: −40°C to 125°C consumes only 14 mW at 2 MSPS with a minimum of 70 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface SCK rate in turbo mode. The AD4004 consumes only 7 mW at Ability to daisy-chain multiple ADCs and busy indicator 1 MSPS with a minimum of 25 MHz SCK rate in turbo mode. Both 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP the AD4000/AD4004 achieve ±1.0 LSB integral nonlinearity error (INL) maximum, no missing codes at 16 bits, and 93 dB signal-to- APPLICATIONS noise ratio (SNR). The reference voltage is applied externally and Automatic test equipment can be set independently of the supply voltage. Machine automation The SPI-compatible versatile serial interface features seven Medical equipment different modes including the ability, using the SDI input, to Battery-powered equipment daisy-chain several ADCs on a single 3-wire bus, and provides an Precision data acquisition systems optional busy indicator. The AD4000/AD4004 are compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD4000/AD4004 are available in a 10-lead MSOP or LFCSP with operation specified from −40°C to +125°C. The devices are pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8). FUNCTIONAL BLOCK DIAGRAM 2.4V TO 5.1V 10µF 1.8V REF VDD VRVERFE/F2 HMIGOHD-EZ AADD44000004/ TMUORDBEO VSIDOI1.8V TO 5V 0 IN+ 16-BIT SERIAL SCK 3-WIRE OR 4-WIRE SAR ADC INTERFACE SDO SPI INTERFACE IN– CLAMPCOMSPPRAENSSON GND STBAITTSUS CNV (DAISY CHAIN, CS)14956-001 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com AD4000/AD4004 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs.............................................................................. 19 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 20 General Description ......................................................................... 1 Ease of Drive Features ............................................................... 20 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 22 Revision History ............................................................................... 2 Power Supply ............................................................................... 22 Specifications ..................................................................................... 3 Digital Interface .......................................................................... 22 Timing Specifications .................................................................. 6 Register Read/Write Functionality........................................... 23 Absolute Maximum Ratings ............................................................ 8 Status Word ................................................................................. 25 Thermal Resistance ...................................................................... 8 CS Mode, 3-Wire Turbo Mode ................................................. 26 ESD Caution .................................................................................. 8 CS Mode, 3-Wire Without Busy Indicator ............................. 27 Pin Configurations and Function Descriptions ........................... 9 CS Mode, 3-Wire with Busy Indicator .................................... 28 Typical Performance Characteristics ........................................... 10 CS Mode, 4-Wire Turbo Mode ................................................. 29 Terminology .................................................................................... 15 CS Mode, 4-Wire Without Busy Indicator ............................. 30 Theory of Operation ...................................................................... 16 CS Mode, 4-Wire with Busy Indicator .................................... 31 Circuit Information .................................................................... 16 Daisy-Chain Mode ..................................................................... 32 Converter Operation .................................................................. 16 Layout Guidelines....................................................................... 33 Transfer Functions...................................................................... 17 Evaluating the AD4000/AD4004 Performance .......................... 33 Applications Information .............................................................. 18 Outline Dimensions ....................................................................... 34 Typical Application Diagrams .................................................. 18 Ordering Guide .......................................................................... 34 REVISION HISTORY 4/2017—Rev. 0 to Rev. A Changes to Long Acquisition Phase Section and Figure 43 ..... 22 Added AD4004 ................................................................... Universal Changes to Digital Interface Section and Register Read/Write Changes to Title, Features Section, General Description Section, Functionality Section ..................................................................... 23 and Figure 1 ....................................................................................... 1 Changes to Figure 45 ...................................................................... 24 Changes to Table 1 ............................................................................ 3 Changes to CS Mode, 3-Wire Turbo Mode Section .................. 26 Changes to Table 2 ............................................................................ 6 Added Figure 48 ............................................................................. 26 Changes to Table 4 ............................................................................ 7 Changes to CS Mode, 4-Wire Turbo Mode ................................ 29 Changes to Table 7 ............................................................................ 9 Added Figure 54 ............................................................................. 29 Changes to Figure 19 and Figure 21 ............................................. 12 Changes to Figure 56 and Figure 57 ............................................ 30 Changes to Figure 24 ...................................................................... 13 Changes to Layout Guidelines Section and Evaluating the Added Figure 25; Renumbered Sequentially .............................. 13 AD4000/AD4004 Performance Section ...................................... 33 Moved Terminology Section ......................................................... 15 Updated Outline Dimensions ....................................................... 34 Changes to Circuit Information Section and Table 8 ................ 16 Changes to Ordering Guide Section ............................................ 34 Changes to Figure 33 ...................................................................... 18 Changes to RC Filters Section ....................................................... 19 10/2016—Revision 0: Initial Version Changes to High Frequency Input Signals Section .................... 20 Changes to High-Z Mode Section, Figure 38, and Figure 39 ... 21 Rev. A | Page 2 of 34 Data Sheet AD4000/AD4004 SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, V = 5 V, all specifications T to T , high-Z mode disabled, span compression disabled, REF MIN MAX turbo mode enabled, and samping frequency (f) = 2 MSPS for the AD4000 and f = 1 MSPS for the AD4004, unless otherwise noted. S S Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V − V 0 V V IN+ IN− REF Operating Input Voltage V to GND −0.1 V + 0.1 V IN+ REF V to GND −0.1 +0.1 V IN− Span compression enabled 0.1 × V 0.9 × V V REF REF Analog Input Current Acquisition phase, T = 25°C 0.3 nA High-Z mode enabled, converting dc 1 µA input at 2 MSPS THROUGHPUT Complete Cycle AD4000 500 ns AD4004 1000 ns Conversion Time 270 290 320 ns Acquisition Phase1 AD4000 290 ns AD4004 790 ns Throughput Rate (f)2 S AD4000 0 2 MSPS AD4004 0 1 MSPS Transient Response3 150 ns DC ACCURACY No Missing Codes 16 Bits Integral Nonlinearity Error (INL) −1.0 ±0.2 +1.0 LSB T = 0°C to 85°C −0.8 ±0.2 +0.8 LSB Differential Nonlinearity Error (DNL) −0.5 ±0.15 +0.5 LSB Transition Noise 0.5 LSB Zero Error −4.5 +4.5 LSB Zero Error Drift4 −0.55 +0.55 ppm/°C Gain Error −20 ±3 +20 LSB Gain Error Drift4 −0.92 +0.92 ppm/°C Power Supply Sensitivity VDD = 1.8 V ± 5% 0.5 LSB 1/f Noise5 Bandwidth = 0.1 Hz to 10 Hz 6 µV p-p AC ACCURACY Dynamic Range 93.5 dB Total RMS Noise 37 µV rms f = 1 kHz, −0.5 dBFS, V = 5 V IN REF Signal-to-Noise Ratio (SNR) 91 93 dB Spurious-Free Dynamic Range (SFDR) 112 dB Total Harmonic Distortion (THD) −115 dB Signal-to-Noise-and-Distortion Ratio 91 92.5 dB (SINAD) Oversampled Dynamic Range Oversampling ratio (OSR) = 256, 117 dB V = 5 V REF Rev. A | Page 3 of 34 AD4000/AD4004 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit f = 1 kHz, −0.5 dBFS, V = 2.5 V IN REF SNR 85.5 87.5 dB SFDR 115 dB THD −113 dB SINAD 85.5 87 dB f = 100 kHz, −0.5 dBFS, V = 5 V IN REF SNR 90 dB THD −95 dB SINAD 89 dB f = 400 kHz, −0.5 dBFS, V = 5 V IN REF SNR 85 dB THD −91 dB SINAD 84 dB −3 dB Input Bandwidth 10 MHz Aperture Delay 1 ns Aperture Jitter 1 ps rms REFERENCE Voltage Range, V 2.4 5.1 V REF Current V = 5 V REF AD4000 2 MSPS 0.75 mA AD4004 1 MSPS 0.325 mA INPUT OVERVOLTAGE CLAMP IN+/IN− Current (I /I ) V = 5 V 50 mA IN+ IN− REF V = 2.5 V 50 mA REF V /V at Maximum I /I V = 5 V 5.4 V IN+ IN− IN+ IN− REF V = 2.5 V 3.1 V REF V /V Clamp On/Off Threshold V = 5 V 5.25 5.4 V IN+ IN− REF V = 2.5 V 2.68 2.8 V REF Deactivation Time 360 ns REF Current at Maximum I V > V 100 µA IN+ IN+ REF DIGITAL INPUTS Logic Levels Input Low Voltage, V VIO > 2.7 V −0.3 +0.3 × VIO V IL VIO ≤ 2.7 V −0.3 +0.2 × VIO V Input High Voltage, V VIO > 2.7 V 0.7 × VIO VIO + 0.3 V IH VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V Input Low Current, I −1 +1 µA IL Input High Current, I −1 +1 µA IH Input Pin Capacitance 6 pF DIGITAL OUTPUTS Data Format Serial 16 bits, straight binary Pipeline Delay Conversion results available immediately after completed conversion Output Low Voltage, V I = 500 µA 0.4 V OL SINK Output High Voltage, V I = −500 µA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD 1.71 1.8 1.89 V VIO 1.71 5.5 V Standby Current VDD and VIO = 1.8 V, T = 25°C 1.6 µA Rev. A | Page 4 of 34 Data Sheet AD4000/AD4004 Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation VDD = 1.8 V, VIO = 1.8 V, V = 5 V REF 10 kSPS, high-Z mode disabled 70 µW 1 MSPS, high-Z mode disabled 7 8.2 mW 2 MSPS, high-Z mode disabled 14 16 mW 1 MSPS, high-Z mode enabled 8 9.9 mW 2 MSPS, high-Z mode enabled 16 19 mW VDD Only 2 MSPS, high-Z mode disabled 9.75 mW 1 MSPS, high-Z mode disabled 4.9 mW REF Only 2 MSPS, high-Z mode disabled 3.75 mW 1 MSPS, high-Z mode disabled 1.9 mW VIO Only 2 MSPS, high-Z mode disabled 0.5 mW 1 MSPS, high-Z mode disabled 0.2 mW Energy per Conversion 7 nJ/sample TEMPERATURE RANGE Specified Performance T to T −40 +125 °C MIN MAX 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4000 and of 1 MSPS for the AD4004. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. The minimum SCK rate required for 1 MSPS operation is 25 MHz with turbo mode enabled. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 18. Rev. A | Page 5 of 34 AD4000/AD4004 Data Sheet TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, V = 5 V, all specifications T to T , high-Z mode disabled, span compression REF MIN MAX disabled, turbo mode enabled, and f = 2 MSPS for the AD4000 and f = 1 MSPS for the AD4004, unless otherwise noted. See Figure 2 for S S the timing voltage levels. Table 2. Digital Interface Timing Parameter Symbol Min Typ Max Unit CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE t 270 290 320 ns CONV ACQUISITION PHASE1 t ACQ AD4000 290 ns AD4004 790 ns TIME BETWEEN CONVERSIONS t CYC AD4000 500 ns AD4004 1000 ns CNV PULSE WIDTH (CS MODE)2 tCNVH 10 ns SCK PERIOD (CS MODE)3 tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK PERIOD (DAISY-CHAIN MODE)4 t SCK VIO > 2.7 V 20 ns VIO > 1.7 V 25 ns SCK LOW TIME t 3 ns SCKL SCK HIGH TIME t 3 ns SCKH SCK FALLING EDGE TO DATA REMAINS VALID DELAY t 1.5 ns HSDO SCK FALLING EDGE TO DATA VALID DELAY t DSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV OR SDI LOW TO SDO D15 MSB VALID DELAY (CS MODE) tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY t 190 ns QUIET1 LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY5 t 60 ns QUIET2 CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tDIS 20 ns SDI VALID SETUP TIME FROM CNV RISING EDGE t 2 ns SSDICNV SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE) tHSDICNV 2 ns SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) t 12 ns HSCKCNV SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) t 2 ns SSDISCK SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) t 2 ns HSDISCK 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4000 and 1 MSPS for the AD4004. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. The minimum SCK rate required for 1 MSPS operation is 25 MHz with turbo mode enabled. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 4 A 50% duty cycle is assumed for SCK. 5 See Figure 22 for SINAD, SNR, and ENOB vs. tQUIET2. Y% VIO1 X% VIO1 tDELAY tDELAY VIH2 VIH2 VIL2 VIL2 12FMSOPINREICM VIUIFOMIC ≤ AV 2TIH.I7 OAVNN, SXD I=MN 8 AT0XA, IABMNLUEDM 1Y V. =IL 2U0S; EFDO.R S VEIEO D >I G2.I7TVA,L X I N=P 7U0T, SAND Y = 30. 14956-002 Figure 2. Voltage Levels for Timing Rev. A | Page 6 of 34 Data Sheet AD4000/AD4004 Table 3. Register Read/Write Timing Parameter Symbol Min Typ Max Unit READ/WRITE OPERATION CNV Pulse Width1 t 10 ns CNVH SCK Period t SCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK Low Time t 3 ns SCKL SCK High Time t 3 ns SCKH READ OPERATION CNV Low to SDO D15 MSB Valid Delay t EN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns SCK Falling Edge to Data Remains Valid t 1.5 ns HSDO SCK Falling Edge to Data Valid Delay t DSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV Rising Edge to SDO High Impedance t 20 ns DIS WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge t 2 ns SSDISCK SDI Valid Hold Time from SCK Rising Edge t 2 ns HSDISCK CNV Rising Edge to SCK Edge Hold Time t 0 ns HCNVSCK CNV Falling Edge to SCK Active Edge Setup Time t 6 ns SCNVSCK 1 For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation Parameter Test Conditions/Comments Min Typ Max Unit THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode f = 100 MHz, VIO ≥ 2.7 V 2 MSPS SCK f = 80 MHz, VIO < 2.7 V 2 MSPS SCK f = 25 MHz, VIO > 1.7 V 1 MSPS SCK 3-Wire and 4-Wire Turbo Mode and Six Status Bits f = 100 MHz, VIO ≥ 2.7 V 2 MSPS SCK f = 80 MHz, VIO < 2.7 V 1.86 MSPS SCK f = 33 MHz, VIO > 1.7 V 1 MSPS SCK 3-Wire and 4-Wire Mode f = 100 MHz, VIO ≥ 2.7 V 1.82 MSPS SCK f = 80 MHz, VIO < 2.7 V 1.69 MSPS SCK f = 27 MHz, VIO > 1.7 V 1 MSPS SCK 3-Wire and 4-Wire Mode and Six Status Bits f = 100 MHz, VIO ≥ 2.7 V 1.64 MSPS SCK f = 80 MHz, VIO < 2.7 V 1.5 MSPS SCK f = 40 MHz, VIO > 1.7 V 1 MSPS SCK Rev. A | Page 7 of 34 AD4000/AD4004 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Note that the input overvoltage clamp cannot sustain the overvoltage condition for an indefinite amount of time. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to Table 5. PCB thermal design is required. Parameter Rating Analog Inputs Table 6. Thermal Resistance IN+, IN− to GND1 −0.3 V to VREF + 0.4 V Package Type1 θJA2 θJC3 Unit or ±50 mA RM-10 147 38 °C/W Supply Voltage CP-10-9 114 33 °C/W REF, VIO to GND −0.3 V to +6.0 V 1 Test Condition 1: thermal impedance simulated values are based upon use VDD to GND −0.3 V to +2.1 V of 2S2P JEDEC PCB. See the Ordering Guide. VDD to VIO −6 V to +2.4 V 2 θJA is the natural convection junction-to-ambient thermal resistance measured in a one cubic foot sealed enclosure. Digital Inputs to GND −0.3 V to VIO + 0.3 V 3 θJC is the junction-to-case thermal resistance. Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C ESD CAUTION Lead Temperature Soldering 260°C reflow as per JEDEC J-STD-020 ESD Ratings Human Body Model 4 kV Machine Model 200 V Field Induced Charged Device Model 1.25 kV 1 See the Analog Inputs section for an explanation of IN+ and IN−. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 8 of 34 Data Sheet AD4000/AD4004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10VIO VDD 2 AD4000/ 9 SDI AD4004 IN+3 8 SCK TOP VIEW REF 1 10 VIO IN– 4 (Not to Scale) 7 SDO VDD 2 AD4000/ 9 SDI GND 5 6 CNV IN+ 3 AD4004 8 SCK GINND– 45 (NToOt Pto V SIEcaWle) 76 SCDNOV 14956-003 N1.OCTMTHOEEINESSTN C ETOCHNTEN TSEHPCEET CEIOIXFNPI EOISDS NEPODER TP FRAOEDRQ TMUOAI RNGECNDED .T.O 14956-004 Figure 3. 10-Lead MSOP Pin Configuration Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 REF AI Reference Input Voltage. The V range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be REF decoupled closely to the GND pin with a 10 µF, X7R ceramic capacitor. 2 VDD P 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. 3 IN+ AI Analog Input. Referred to analog ground sense pin (IN−). The device samples the voltage differential between IN+ and IN− on the leading edge on CNV. The operating input range of IN+ − IN− is 0 V to V . REF 4 IN− AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on the rising edge of SCK. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. N/A2 EPAD P Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet the specified performance. 1 AI is analog input, P is power, DI is digital input, and DO is digital output. 2 N/A means not applicable. Rev. A | Page 9 of 34 AD4000/AD4004 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 1.8 V, VIO = 3.3 V, V = 5 V, T = 25°C, high-Z mode disabled, span compression disabled, turbo mode enabled, and f = 2 MSPS REF S for the AD4000 and f = 1 MSPS for the AD4004, unless otherwise noted. S 0.5 0.20 +125°C 0.4 +25°C –40°C 0.15 0.3 0.10 0.2 0.05 B) 0.1 B) NL (LS 0 NL (LS 0 I –0.1 D –0.05 –0.2 –0.10 –0.3 –0.15 +125°C –0.4 +25°C –40°C –0.50 8192 16384 24576 C32O7D68E 40960 49152 57344 65536 14956-200 –0.200 8192 16384 24576 C32O7D68E 40960 49152 57344 65536 14956-203 Figure 5. INL vs. Code and Temperature, VREF = 5 V Figure 8. DNL vs. Code and Temperature, VREF = 5 V 0.3 0.20 +125°C +25°C –40°C 0.15 0.2 0.10 0.1 0.05 B) B) NL (LS 0 NL (LS 0 I D –0.05 –0.1 –0.10 –0.2 –0.15 +125°C +25°C –40°C –0.30 8192 16384 24576 C32O7D68E 40960 49152 57344 65536 14956-201 –0.200 8192 16384 24576 C32O7D68E 40960 49152 57344 65536 14956-204 Figure 6. INL vs. Code and Temperature, VREF = 2.5 V Figure 9. DNL vs. Code and Temperature, VREF = 2.5 V 0.4 0.20 0.3 0.15 0.2 0.10 0.1 0.05 B) B) S S NL (L 0 NL (L 0 I D –0.1 –0.05 –0.2 –0.10 –0.3 SPAN COMPRESSION ENABLED –0.15 SPAN COMPRESSION ENABLED HIGH-Z ENABLED HIGH-Z ENABLED –0.40 8192 16384 24576 C32O7D68E 40960 49152 57344 65536 14956-202 –0.200 8192 16384 24576 C32O7D68E 40960 49152 57344 65536 14956-205 Figure 7. INL vs. Code, High-Z and Span Compression Enabled, VREF = 5 V Figure 10. DNL vs. Code, High-Z and Span Compression Enabled, VREF = 5 V Rev. A | Page 10 of 34