12-Bit High-Speed, Multiple SARs A/D Converter (ADC) HIGHLIGHTS This section of the manual contains the following major topics: 1.0 Introduction.......................................................................................................................2 2.0 Registers...........................................................................................................................5 3.0 Conversion Sequence.....................................................................................................36 4.0 ADC Operation................................................................................................................36 5.0 Application Examples......................................................................................................57 6.0 Operation During Power-Saving Modes.........................................................................70 7.0 Effects of Reset...............................................................................................................70 8.0 Register Map...................................................................................................................71 9.0 Related Application Notes...............................................................................................75 10.0 Revision History..............................................................................................................76 © 2014-2017 Microchip Technology Inc. DS70005213F-page 1 dsPIC33/PIC24 Family Reference Manual Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on the device variant, this manual section may not apply to all dsPIC33/PIC24 devices. Please consult the note at the beginning of the chapter in the specific device data sheet to check whether this document supports the device you are using. Device data sheets and family reference manual sections are available for download from the Microchip Worldwide Web site at: http://www.microchip.com. 1.0 INTRODUCTION The dsPIC33/PIC24 12-Bit High-Speed, Multiple SARs Analog-to-Digital Converter (ADC) includes the following features: • Multiple ADC Cores: - Multiple single channel dedicated ADC cores (depending on the specific device implementation) - One shared (common) ADC core • Configurable 6, 8, 10 or 12-Bit Resolution for each ADC Core • Up to 3.25 Msps Conversion Rate per Channel for 12-Bit Resolution • Up to 32 Analog Input Sources (depending on the specific device implementation) • Single-Ended or Pseudodifferential Inputs on a per Channel Basis for All Channels • Conversion Result can be Formatted as Unsigned or Signed Data on a per Channel Basis for All Channels • Separate 16-Bit Conversion Result Register for each Analog Input • Early Interrupt Generation to enable Fast Processing of Converted Data • Multiple Integrated Digital Comparators (depending on the specific device implementation): - Multiple comparison options - Assignable to specific analog inputs • Multiple Oversampling Filters (depending on the specific device implementation): - Provides increased resolution - Assignable to a specific analog input • Operation during CPU Sleep and Idle modes • Hardware Capacitive Voltage Divider (CVD) to Measure Capacitance Connected to the Input Simplified block diagrams of the Multiple SARs 12-Bit ADC are illustrated in Figure1-1, Figure1-2 and Figure1-3. The module consists of a few independent SAR ADC cores. The analog inputs (channels) are connected through multiplexers and switches to the Sample-and-Hold (S/H) circuit of each ADC core. The core uses the channel information (output format, Measurement mode and input number) to process the analog sample. When conversion is complete, the result is stored in the result buffer for the specific analog input, and passed to the digital filter and digital comparator if they were configured to use data from this particular channel. DS70005213F-page 2  2014-2017 Microchip Technology Inc. 12-Bit High-Speed, Multiple SARs A/D Converter (ADC) Figure 1-1: 12-Bit High-Speed, Multiple SARs ADC Block Diagram AVDD AVSSVREF+VREF-INTREF Reference Voltage Selection (REFSEL<2:0> bits) Reference Analog Inputs Dedicated ADC Output Data Core 0 ((Sseeee FFiigguurree 11--22)) Digital Comparator 0 Clock ADCMP0Interrupt Digital Comparator x ADCMPxInterrupt Reference Analog Inputs Dedicated ADC Output Data Core 1 Digital Filter 0 ADFL0DAT ADFL0Interrupt ((sSeeee FFiigguurree 11--22)) Clock Digital Filter x ADFLxDAT ADFLxInterrupt ADCBUF0 Reference ADCAN0Interrupt Analog ADCBUF1 ADCAN1Interrupt Inputs Output Data Shared ADC Core ((Sseeee FFiigguurree 11--33)) Clock ADCBUFx ADCANxInterrupt Clock Source Divider (CLKDIV<5:0> bits) Clock Source Selection (CLKSEL<1:0> bits) Instruction FRC Fosc AUX Clock Clock  2014-2017 Microchip Technology Inc. DS70005213F-page 3 dsPIC33/PIC24 Family Reference Manual Figure 1-2: Dedicated ADC Core ANx Analog Input “+” Pins Positive Input Selection Reference (CxCHS<1:0> From Other bits) 12-Bit SAR Analog Sample- ADC Output Data Modules and-Hold ANy Negative Input “–” Selection ADC Core (DIFFx bit) Clock Clock Divider (ADCS<6:0> Trigger Stops bits) Sampling AVSS Figure 1-3: Shared ADC Core ANx Shared ADC Core Analog Input Pins “+” Reference From Other 12-Bit SAR Analog ADC Output Data Modules Shared Analog Channel Number Sample- from Current Trigger and-Hold ADC Core Clock Clock ANy Divider Negative (SHRADCS<6:0> Input “–” bits) Selection (DIFFx bit) Sampling Time is Defined by SHRSAMC<8:0> bits AVSS DS70005213F-page 4  2014-2017 Microchip Technology Inc. 12-Bit High-Speed, Multiple SARs A/D Converter (ADC) 2.0 REGISTERS The Special Function Registers (SFRs) of the 12-Bit High-Speed, Multiple SARs ADC module are divided into two groups: control registers and data registers. A complete list of all SFRs implemented by the ADC is provided in Table8-1. 2.1 Control Registers The ADCON1L register (Register2-1) contains bits to enable the module, define the module behavior in Idle mode and enable the CVD feature. The ADCON1H register (Register2-2) controls the output data format and the shared ADC core resolution. The ADCON2L register (Register2-3) controls the clock divider and early interrupt timing selection for the shared ADC core. It has bits to enable the common interrupt for the events related to the voltage reference and a bit to enable an early interrupt feature for the individual input channels. The ADCON2H register (Register2-4) controls the sampling time for the shared ADC core. It also provides the status bits, which indicate that the module voltage reference is ready for operation. This register allows adjusting the internal capacitance value for the CVD feature. The ADCON3L register (Register2-5) selects the voltage reference for all ADC cores and controls common, level and single-shot software triggers. Also, it has control bits to suspend all triggers for the module. The ADCON3H register (Register2-6) has bits to enable all ADC cores and select a clock source for the module. Also, this register controls the module clock source divider. The ADCON4L register (Register2-7) allows enabling a delay between trigger and conversion for the dedicated ADC cores, and triggers synchronization. The ADCON4H register (Register2-8) selects channels for the dedicated ADC cores. The ADCON5L register (Register2-9) controls power for all ADC cores. The ADCON5H register (Register2-10) has bits to enable a common interrupt for each ADC core when it is powered on and ready for operation. Also in this register, the power-on delay is specified for all ADC cores. The ADCOREnL (where ‘n’ is a dedicated ADC core number) registers (Register2-11) define a delay between trigger and conversion for each dedicated ADC core. The ADCOREnH (where ‘n’ is a dedicated ADC core number) registers (Register2-12) define resolution, early interrupt time selection and the ADC core clock divider for each dedicated ADC core. The ADLVLTRGL and ADLVLTRGH registers (Register2-13 and Register2-14) have bits to select either the level-sensitive trigger or the edge-sensitive trigger for each input channel. The ADEIEL and ADEIEH registers (Register2-15 and Register2-16) have bits to enable the early interrupts generation for each input channel. The ADEISTATL and ADEISTATH registers (Register2-17 and Register2-18) contain the early interrupts status flags for each input channel. The ADMOD0L, ADMOD0H, ADMOD1L and ADMOD1H registers (Register2-19 through Register2-22) have bits to enable the Pseudodifferential mode and signed output data format for each input channel. The ADIEL and ADIEH registers (Register2-23 and Register2-24) have bits to enable the individual and common interrupts for each input channel. The ADSTATL and ADSTATH registers (Register2-25 and Register2-26) contain the data ready flags for each input channel. The ADTRIGnL and ADTRIGnH registers (Register2-27) define a trigger source for each input channel. The ADCAL0L, ADCAL0H, ADCAL1L and ADCAL1H registers (Register2-28 through Register2-31) control the calibration for each ADC core. The calibration is not required for some devices. Refer to the specific device data sheet to see if these registers are implemented.  2014-2017 Microchip Technology Inc. DS70005213F-page 5 dsPIC33/PIC24 Family Reference Manual The ADCMPnCON registers (Register2-32) control the operation of the digital comparators, including the generation of the interrupts and the comparison criteria to be used. These registers also provide the status when a comparator event occurs. One register is provided for each digital comparator. The ADCMPnENL and ADCMPnENH registers (Register2-33 and Register2-34) select which of the analog input conversion results are to be processed by the digital comparator. One pair (Land H) is provided for each digital comparator. The ADFLnCON registers (Register2-35) control the operation of the oversampling filters and provide status bits for the filters’ operation. One register is provided for each oversampling filter. The ADCSSL and ADCSSH registers (Register2-36 and Register2-37) select which of the analog inputs are to be scanned/processed by the CVD. 2.2 Data Registers The ADCBUFx registers store the output data of the Analog-to-Digital conversion. In general, there is one register provided for each of the implemented analog channels; each channel will have a corresponding numbered ADCBUFx register. Although the registers are 16 bits wide, the usage of the registers for storing the 12-bit conversion results is determined by the selected data output format. See Section4.10 “Conversion Result” for more information. The ADCMPnLO and ADCMPnHI registers store the 16-bit high and low digital comparison values for use by the digital comparators. One pair (HI and LO) is provided for each ADC comparator. The ADFLnDAT registers contain the 16-bit output data from the oversampling filters. There is one register for each oversampling filter. The ADCVDDAT register contains the 16-bit output data from the Capacitive Voltage Divider (CVD). This register may not be implemented on some devices. Refer to the specific device data sheet to see if the CVD feature is implemented on the device. DS70005213F-page 6  2014-2017 Microchip Technology Inc. 12-Bit High-Speed, Multiple SARs A/D Converter (ADC) Register 2-1: ADCON1L: ADC Control Register 1 Low R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 ADON(1) — ADSIDL — CVDEN(2) — — — bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NRE(3) — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Enable bit(1) 1 = ADC module is enabled 0 = ADC module is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: ADC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 CVDEN: CVD Enable bit(2) 1 = CVD is enabled 0 = CCD is off bit 10-8 Unimplemented: Read as ‘0’ bit 7 NRE: Noise Reduction Enable bit(3) 1 = Holds conversion process for 1 TADCORE when another core completes conversion to reduce noise between cores 0 = Noise Reduction feature is disabled bit 6-0 Unimplemented: Read as ‘0’ Note 1: Set the ADON bit only after the ADC module has been configured. Changing ADC Configuration bits when ADON = 1 will result in unpredictable behavior. 2: The CVD feature is not available on all devices and the CVDEN bit may not be implemented. Refer to the device data sheet for more information. 3: The Noise Reduction feature is not available on all devices and the NRE bit may not be implemented. Refer to the device data sheet for more information.  2014-2017 Microchip Technology Inc. DS70005213F-page 7 dsPIC33/PIC24 Family Reference Manual Register 2-2: ADCON1H: ADC Control Register 1 High r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-1 R/W-1 r-0 r-0 r-0 r-0 r-0 FORM SHRRES1 SHRRES0 — — — — — bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Reserved: Must be written as ‘0’ bit 7 FORM: Fractional Data Output Format bit 1 = Fractional 0 = Integer bit 6-5 SHRRES<1:0>: Shared ADC Core Resolution Selection bits 11 = 12-bit resolution 10 = 10-bit resolution 01 = 8-bit resolution 00 = 6-bit resolution bit 4-0 Reserved: Must be written as ‘0’ DS70005213F-page 8  2014-2017 Microchip Technology Inc. 12-Bit High-Speed, Multiple SARs A/D Converter (ADC) Register 2-3: ADCON2L: ADC Control Register 2 Low R/W-0 R/W-0 r-0 R/W-0 r-0 R/W-0 R/W-0 R/W-0 REFCIE REFERCIE(2) — EIEN — SHREISEL2(1) SHREISEL1(1) SHREISEL0(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SHRADCS6 SHRADCS5 SHRADCS4 SHRADCS3 SHRADCS2 SHRADCS1 SHRADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 REFCIE: Band Gap and Reference Voltages Ready Common Interrupt Enable bit 1 = Common interrupt will be generated when band gap and reference voltage are ready 0 = Common interrupt is disabled for band gap and reference voltage ready event bit 14 REFERCIE: Band Gap and Reference Voltages Error Common Interrupt Enable bit(2) 1 = Common interrupt will be generated when band gap or reference voltage error is detected 0 = Common interrupt is disabled for band gap and reference voltages error event bit 13 Reserved: Must be written as ‘0’ bit 12 EIEN: Early Interrupts Enable bit 1 = The early interrupt feature is enabled for the input channel interrupts (when the EISTATx flag is set) 0 = The individual interrupts are generated when the conversion is done (when the ANxRDY flag is set) bit 11 Reserved: Must be written as ‘0’ bit 10-8 SHREISEL<2:0>: Shared Core Early Interrupt Time Selection bits(1) 111 = Early interrupt is generated 8 TADCORE clocks prior to when the data is ready 110 = Early interrupt is generated 7 TADCORE clocks prior to when the data is ready 101 = Early interrupt is generated 6 TADCORE clocks prior to when the data is ready 100 = Early interrupt is generated 5 TADCORE clocks prior to when the data is ready 011 = Early interrupt is generated 4 TADCORE clocks prior to when the data is ready 010 = Early interrupt is generated 3 TADCORE clocks prior to when the data is ready 001 = Early interrupt is generated 2 TADCORE clocks prior to when the data is ready 000 = Early interrupt is generated 1 TADCORE clock prior to when the data is ready bit 7 Unimplemented: Read as ‘0’ bit 6-0 SHRADCS<6:0>: Shared ADC Core Input Clock Divider bits These bits determine the number of TCORESRC (Source Clock Periods) for one shared TADCORE (Core Clock Period). 1111111 = 254 source clock periods • • • 0000011 = 6 source clock periods 0000010 = 4 source clock periods 0000001 = 2 source clock periods 0000000 = 2 source clock periods Note 1: For the 6-bit shared ADC core resolution (SHRRES<1:0> = 00), the SHREISEL<2:0> settings, from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit shared ADC core resolution (SHRRES<1:0> = 01), the SHREISEL<2:0> settings, ‘110’ and ‘111’, are not valid and should not be used. 2: To avoid false interrupts, the REFERCIE bit must be set only after the module is enabled (ADON = 1).  2014-2017 Microchip Technology Inc. DS70005213F-page 9 dsPIC33/PIC24 Family Reference Manual Register 2-4: ADCON2H: ADC Control Register 2 High R/HS/HC-0 R/HS/HC-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 REFRDY REFERR — CVDCAP2(1) CVDCAP1(1) CVDCAP0(1) SHRSAMC9 SHRSAMC8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SHRSAMC7 SHRSAMC6 SHRSAMC5 SHRSAMC4 SHRSAMC3 SHRSAMC2 SHRSAMC1 SHRSAMC0 bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 REFRDY: Band Gap and Reference Voltages Ready Flag bit 1 = Band gap and reference voltages are ready 0 = Band gap and reference voltages are not ready bit 14 REFERR: Band Gap or Reference Voltage Error Flag bit 1 = Band gap or reference voltage was interrupted after the ADC module was enabled (ADON = 1) 0 = No band gap or reference voltage error was detected bit 13 Reserved: Must be written as ‘0’ bit 12-10 CVDCAP<2:0>: CVD Additional Capacitance Selection bits(1) This capacitance is added to the shared core Sample-and-Hold Capacitance (CHOLD) when CVD is enabled. 111 = 7 * 2.5 pF = 17.5 pF 110 = 6 * 2.5 pF = 15 pF 101 = 5 * 2.5 pF = 12.5 pF 100 = 4 * 2.5 pF = 10 pF 011 = 3 * 2.5 pF = 7.5 pF 010 = 2 * 2.5 pF = 5 pF 001 = 1 * 2.5 pF = 2.5 pF 000 = 0 * 2.5 pF = 0 pF bit 9-0 SHRSAMC<2:0>: Shared ADC Core Sample Time Selection bits These bits specify the number of shared Core Clock Periods (TADCORE) for the shared ADC core sample time. 1111111111 = 1025 TADCORE • • • 0000000001 = 3 TADCORE 0000000000 = 2 TADCORE Note 1: The CVD feature is not available on all devices and the CVDCAP<2:0> bits may not be implemented. Refer to the device data sheet for more information. DS70005213F-page 10  2014-2017 Microchip Technology Inc.