User’s Manual, V2.0, Mar. 2001 I n s t r u c t i o n S e t M a n u a l for the C166 Family of Infineon 16-Bit Single-Chip Microcontrollers Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2001-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. User’s Manual, V2.0, Mar. 2001 I n s t r u c t i o n S e t M a n u a l for the C166 Family of Infineon 16-Bit Single-Chip Microcontrollers Microcontrollers N e v e r s t o p t h i n k i n g . C166 Family Microcontroller Instruction Set Manual Revision History: V2.0, 2001-03 Previous Version: Version 1.2, 12.97 Version 1.1, 09-95 03.94 Page Subjects (major changes since last revision) all Converted to new company layout 4 … 30 Overview- and summary-tables reformatted 2 List of derivatives updated 31 Description template added 34 PSW image added 38 Condition code table moved 40 Note for MUL/DIV added 42ff Immediate data for byte instructions corrected to #data8 52f Note improved 62 Description of operation corrected 72ff Description of division instructions improved 85 Format description corrected 86 Description improved 101f Description of multiplication instructions improved 128 Description of flags corrected 132 “bitoff” for ESFRs added 137 Section moved 139 Target address for “rel” corrected 141 General description improved 142ff Timing examples converted to 25 MHz 143 Branch execution times corrected 148f Keyword index introduced We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] C166 Family Instruction Set Table of Contents Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Overviews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Data Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Branch Target Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Multiply and Divide Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Extension Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Branch Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.1 Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.2 Long Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.4 DPP Override Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.5 Constants within Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.6 Instruction Range (#irang2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.7 Branch Target Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.1 Time Unit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.2 Minimum Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.3 Additional State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8 Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 User’s Manual V2.0, 2001-03 C166 Family Instruction Set Introduction 1 Introduction The Infineon C166 Family of 16-bit microcontrollers offers devices that provide various levels of peripheral performance and programmability. This allows to equip each specific application with the microcontroller that fits best to the required functionality and performance. Still the Infineon family concept provides an easy path to upgrade existing applications or to climb the next level of performance in order to realize a subsequent more sophisticated design. Two major characteristics enable this upgrade path to save and reuse almost all of the engineering efforts that have been made for previous designs: (cid:127) All family members are based on the same basic architecture (cid:127) All family members execute the same instructions (except for upgrades for new members) The fact that all members execute basically the same instructions saves know-how with respect to the understanding of the controller itself and also with respect to the used tools (assembler, disassembler, compiler, etc.). This instruction set manual provides an easy and direct access to the instructions of the Infineon 16-bit microcontrollers by listing them according to different criteria, and also unloads the technical manuals for the different devices from redundant information. This manual also describes the different addressing mechanisms and the relation between the logical addresses used in a program and the resulting physical addresses. There is also information provided to calculate the execution time for specific instructions depending on the used address locations and also specific exceptions to the standard rules. Description Levels In the following sections the instructions are compiled according to different criteria in order to provide different levels of precision: (cid:127) Cross Reference Tables summarize all instructions in condensed tables (cid:127) The Instruction Set Summary groups the individual instructions into functional groups (cid:127) The Opcode Table references the instructions by their hexadecimal opcode (cid:127) The Instruction Description describes each instruction in full detail User’s Manual 1 V2.0, 2001-03 C166 Family Instruction Set Introduction All instructions listed in this manual are executed by the following devices (new derivatives will be added to this list): (cid:127) C161K, C161O, C161PI (cid:127) C161CS, C161JC, C161JI (cid:127) C163 (cid:127) C164CI, C164SI, C164CM, C164SM (cid:127) C165 (cid:127) C167CR, C167SR (cid:127) C167CS A few instructions (ATOMIC and EXTended instructions) have been added for these devices and are not recognized by the following devices from the first generation of 16- bit microcontrollers: (cid:127) SAB 80C166, SAB 80C166W (cid:127) SAB 83C166, SAB 83C166W These differences are noted for each instruction, where applicable. User’s Manual 2 V2.0, 2001-03 C166 Family Instruction Set Overviews 2 Overviews The following compressed cross-reference tables quickly identify a specific instruction and provide basic information about it. Two ordering schemes are included: (cid:127) The hexadecimal opcode of a specific instruction can be quickly identified with the respective mnemonic using the first compressed cross-reference table. (cid:127) The mnemonics and addressing modes of the various instructions are listed in the second table. The table shows which addressing modes may be used with a specific instruction and also the instruction length depending on the selected addressing mode. This reference helps to optimize instruction sequences in terms of code size and/or execution time. Both ordering schemes (hexadecimal opcode and mnemonic) are provided in more detailed lists in the following sections of this manual. Note: The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices. They are marked in the cross-reference table. User’s Manual 3 V2.0, 2001-03 C166 Family Instruction Set Overviews Table 1 Instruction Overview ordered by Hex-Code (lower half) 0x 1x 2x 3x 4x 5x 6x 7x x0 ADD ADDC SUB SUBC CMP XOR AND OR x1 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x2 ADD ADDC SUB SUBC CMP XOR AND OR x3 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x4 ADD ADDC SUB SUBC – XOR AND OR x5 ADDB ADDCB SUBB SUBCB – XORB ANDB ORB x6 ADD ADDC SUB SUBC CMP XOR AND OR x7 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x8 ADD ADDC SUB SUBC CMP XOR AND OR x9 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB xA BFLDL BFLDH BCMP BMOVN BMOV BOR BAND BXOR xB MUL MULU PRIOR – DIV DIVU DIVL DIVLU xC ROL ROL ROR ROR SHL SHL SHR SHR xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR xF BSET BSET BSET BSET BSET BSET BSET BSET User’s Manual 4 V2.0, 2001-03 C166 Family Instruction Set Overviews Table 2 Instruction Overview ordered by Hex-Code (upper half) 8x 9x Ax Bx Cx Dx Ex Fx x0 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS MOV MOV ATOMIC x1 NEG CPL NEGB CPLB – MOVB MOVB EXTR x2 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS PCALL MOV x3 – – – – – – – MOVB x4 MOV MOV MOVB MOVB MOV MOV MOVB MOVB x5 – – DISWDT EINIT MOVBZ MOVBS – – x6 CMPI1 CMPI2 CMPD1 CMPD2 SCXT SCXT MOV MOV EXTP[R] x7 IDLE PWRDN SRVWDT SRST – MOVB MOVB EXTS[R] x8 MOV MOV MOV MOV MOV MOV MOV – x9 MOVB MOVB MOVB MOVB MOVB MOVB MOVB – xA JB JNB JBC JNBS CALLA CALLS JMPA JMPS xB – TRAP CALLI CALLR RET RETS RETP RETI EXTP[R] xC – JMPI ASHR ASHR NOP PUSH POP EXTS[R] xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR xF BSET BSET BSET BSET BSET BSET BSET BSET User’s Manual 5 V2.0, 2001-03