DESIGN OF LOW-COST HIGH-ACCURACY MICROCONTROLLER-BASED RESOLVER EMULATOR A Thesis Presented to The Graduate Faculty of The University of Akron In Partial Fulfillment of the Requirements for the Degree Master of Science Pongpachara Limpisathian December, 2013 DESIGN OF LOW-COST HIGH-ACCURACY MICROCONTROLLER-BASED RESOLVER EMULATOR Pongpachara Limpisathian Thesis Approved: Accepted: ____________________ ____________________ Co-Advisor Department Chair Dr. Joan E. Carletta Dr. Alex De Abreu-Garcia ____________________ ____________________ Co-Advisor Dean of the College Dr. Kye-Shin Lee Dr. George K. Haritos ____________________ ____________________ Committee Member Dean of the Graduate School Dr. Robert Veillette Dr. George R. Newkome ____________________ Date ii ABSTRACT This thesis presents an architecture and analysis of a resolver emulator using a microcontroller and a multiplying digital-to-analog converter. The proposed resolver emulator architecture is designed to achieve output accuracy similar to commercially available resolver emulators but at a lower cost and complexity. A microcontroller is used to compute and store the sine and cosine representations of the digital input positions and a multiplying digital-to-analog converter is used to modulate the reference carrier with the sine and cosine representations into corresponding resolver emulator outputs. The pertinent design parameters are the number of digital input position bits, the number of multiplier bits, and the rate at which updates are communicated to the multiplying digital- to-analog converter. Simulation results show an improvement of nearly 20 arcminutes in the total error is observed as the number of multiplier bits is increased from 8 to 14 bits when the number of digital input bits is 16. The update rate should be at least 360 times larger than the rate of shaft rotation. An experimental test bench is constructed to gain further insight into the non-idealities of the resolver emulator. The results show that the implemented resolver emulator with 16 digital input position bits, 14 multiplier bits, and an update rate of 16 kHz realized an average error magnitude of approximately 32 arcminutes. The packaging and design of the analog backend can be improved to eliminate noise and allow an output accuracy of within 10 arcminutes. iii ACKNOWLEDGEMENTS I would like to thank my parents, Saritpong and Patcharee, for the supports they have given me over the years; none of this would have been possible without their supports. I also would like to thank Uea-issara Thanatwaranon for always supporting and cheering me up when things get tough. I sincerely thank my advisors and my committee member, Dr Joan Carletta, Dr Kye-Shin Lee, and Dr Robert Veillette, for their invaluable guidance and support throughout the years. I could not possibly express enough gratitude to them for everything that they have done for me. Special thanks to Mrs Gay Boden and the Department of Electrical and Computer Engineering. Lastly, I would like to thank all of my friends here at the University of Akron including Joseph Davis, Kripesh Bhattarai, Jian Liu, Purushottam Parajuli, Shivasai Bethi, Michelle Liu, Mike Willett, Shilpa Chakinala, and Sneha Bhattaram. iv TABLE OF CONTENTS Page LIST OF TABLES ........................................................................................................... viii LIST OF FIGURES ........................................................................................................... ix CHAPTER I. INTRODUCTION ........................................................................................................... 1 1.1 Motivation ................................................................................................................. 1 1.2 Goal and contribution of thesis ................................................................................. 3 1.3 Organization of thesis................................................................................................ 4 II. RESOLVER AND RESOLVER EMULATOR BACKGROUND ............................... 5 2.1 Feedback position sensors ......................................................................................... 5 2.1.1 Incremental encoders .......................................................................................... 6 2.1.2 Absolute encoders............................................................................................... 9 2.1.3 Resolvers .......................................................................................................... 11 2.1.4 Synchros ........................................................................................................... 16 2.2 Resolver conversions............................................................................................... 18 2.2.1 Resolver-to-digital converters .......................................................................... 18 2.2.2 Resolver emulators ........................................................................................... 21 2.3 Summary ................................................................................................................. 22 v III. ANALYSIS OF RESOLVER EMULATOR ARCHITECTURES ............................ 24 3.1 Specifications of the resolver emulator ................................................................... 24 3.2 Architectures considered for the resolver emulator ................................................ 27 3.2.1 Weighted resistor-ratio network with amplitude modulation ........................... 28 3.2.2 Microcontroller with pulse-width modulation, low-pass filters and multipliers .................................................................................................................. 31 3.2.3 Microcontroller with digital-to-analog converters and multipliers .................. 33 3.3 Microcontroller with a multiplying digital-to-analog converter ............................. 35 3.4 Summary ................................................................................................................. 37 IV. SIMULATION OF PROPOSED ARCHITECTURE FOR RESOLVER EMULATOR .................................................................................................................... 38 4.1 Analysis of sources of error .................................................................................... 38 4.1.1 Quantization error in the digital input position ................................................ 39 4.1.2 Quantization error in the sine and cosine computation .................................... 40 4.1.3 Error due to finite rate of update of the multiplying digital-to-analog converter .................................................................................................................... 42 4.2 Resolver emulator simulated ................................................................................... 44 4.3 Simulation method .................................................................................................. 45 4.4 Illustration of the effect of quantization on the sine and cosine of the shaft angle . 48 4.5 Effect of the quantized sine and cosine on the forward and reverse ramp simulations .................................................................................................................... 53 4.6 Analysis of the total error of the forward ramp and the reverse ramp simulations . 58 4.7 Summary ................................................................................................................. 70 V. TEST RESULTS FOR THE IMPLEMENTED RESOLVER EMULATOR .............. 75 vi 5.1 The implemented resolver emulator ........................................................................ 75 5.2 Experimental test bench setup ................................................................................. 80 5.3 Test to determine baseline noise and dc offset ........................................................ 83 5.4 Tests of output accuracy .......................................................................................... 85 5.5 Output settling time ................................................................................................. 91 5.6 Summary ................................................................................................................. 93 VI. CONCLUSIONS ........................................................................................................ 99 6.1 Summary ................................................................................................................. 99 6.2 Recommendations ................................................................................................. 100 6.3 Future research ...................................................................................................... 102 BIBLIOGRAPHY ........................................................................................................... 104 vii LIST OF TABLES Table Page 2.1: Quadrant selector of resolver outputs ........................................................................ 15 3.1: Specifications for the resolver emulator .................................................................... 27 3.2: Comparison of resolver emulator architectures ......................................................... 36 4.1: Summary of total errors of forward ramp simulation ................................................ 61 4.2: Summary of total errors of reverse ramp simulation ................................................. 64 5.1: Summary of error from bench testing results for a shaft angle of 125°..................... 88 5.2: Summary of error from bench testing results for a shaft angle of 310°..................... 90 5.3: Output settling time of the resolver emulator ............................................................ 94 viii LIST OF FIGURES Figure Page 1.1: Block diagram of a position feedback system ............................................................. 2 2.1: Quadrature pulses (A, B) and home pulse (Z) of an incremental encoder with eight sectors [8] ............................................................................................................................ 8 2.2: Incremental encoder disc pattern with eight sectors [8] .............................................. 9 2.3: Absolute encoder disc pattern with 1024 sectors [11] ............................................... 11 2.4: Rotor and stators placement of a resolver .................................................................. 14 2.5: Single-ended outputs of resolver as a function of the shaft angle [13] ...................... 15 2.6: Rotor and stator placement of a synchro ................................................................... 17 2.7: Block diagram of a position feedback system with a resolver-to-digital converter or a resolver emulator .............................................................................................................. 19 2.8: Block diagram of a single RC phase-shift resolver-to-digital converter ................... 20 3.1: An example of an n-bit weighted resistor-ratio network [20] ................................... 30 3.2: Architecture using weighted resistor-ratio networks with amplitude modulation ..... 30 3.3: Architecture using microcontroller with pulse-width modulation, low-pass filters and multipliers ......................................................................................................................... 31 3.4: Architecture using microcontroller with digital-to-analog converters and multipliers ........................................................................................................................................... 34 3.5: Architecture using microcontroller with mDAC ....................................................... 36 4.1: Sources of error in the proposed resolver emulator architecture ............................... 39 4.2: Sine and cosine representations and ideal resolver emulator outputs for forward ramp simulation with a reference carrier frequency of 20 Hz and a rotation speed of 1 Hz ..... 47 ix 4.3: Plots of the sine versus cosine for the forward ramp simulation ............................... 50 4.4: First zoomed-in version of plots of the sine versus cosine for the forward ramp simulation .......................................................................................................................... 51 4.5: Second zoomed-in version of plots of the sine versus cosine for the forward ramp simulation .......................................................................................................................... 52 4.6: Actual and quantized input positions of the first 20 discrete time steps of the forward ramp simulation for 16-bit digital input position .............................................................. 56 4.7: Actual and quantized sine representations of the first 20 discrete time steps of the forward ramp simulation for 14-bit multiplier and 16-bit digital input position .............. 57 4.8: Actual and quantized input positions of the last 20 discrete time steps of the reverse ramp simulation for 16-bit digital input position .............................................................. 57 4.9: Actual and quantized sine representations of the first 20 discrete time steps of the reverse ramp simulation for 14-bit multiplier and 16-bit digital input position ............... 58 4.10: Shaft angle of the resolver emulator for the forward ramp simulation .................... 61 4.11: Zoomed-in version of resolver emulator output for the forward ramp simulation .. 62 4.12: Absolute errors of resolver emulator output for the forward ramp simulation ........ 63 4.13: Shaft angle of the resolver emulator output for the reverse ramp simulation .......... 64 4.14: Zoomed-in version of resolver emulator output for the reverse ramp simulation ... 65 4.15: Absolute errors of resolver emulator output for the reverse ramp simulation ......... 66 4.16: Average and range of total error for the forward ramp simulation .......................... 71 4.17: Average magnitude of total error for the forward ramp simulation ........................ 72 4.18: Average and range of total error for the reverse ramp simulation ........................... 73 4.19: Average magnitude of total error for the reverse ramp simulation .......................... 74 5.1: The implemented resolver emulator .......................................................................... 77 5.2: Timing diagram of the communications between the microcontroller and the multiplying digital-to-analog converter ............................................................................ 77 5.3: Implemented resolver emulator ................................................................................. 78 x