ANALYSIS AND DESIGN OF A SCALABLE DIGITAL INPUT CLASS D AUDIO AMPLIFIER TOPOLOGY By Anthony Forzley, B. Sc., M. Sc. A thesis submitted to the Faculty of Graduate and Postdoctoral Affairs in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in ELECTRICAL AND COMPUTER ENGINEERING Ottawa-Carleton Institute for Electrical and Computer Engineering Carleton University Department of Electronics © Anthony Forzley, 2013 1+1 Library and Archives Bibliotheque et Canada Archives Canada Published Heritage Direction du Branch Patrimoine de I'edition 395 Wellington Street 395, rue Wellington Ottawa ON K1A0N4 Ottawa ON K1A 0N4 Canada Canada Your file Votre reference ISBN: 978-0-494-94215-4 Our file Notre reference ISBN: 978-0-494-94215-4 NOTICE: AVIS: The author has granted a non­ L'auteur a accorde une licence non exclusive exclusive license allowing Library and permettant a la Bibliotheque et Archives Archives Canada to reproduce, Canada de reproduire, publier, archiver, publish, archive, preserve, conserve, sauvegarder, conserver, transmettre au public communicate to the public by par telecommunication ou par I'lnternet, preter, telecommunication or on the Internet, distribuer et vendre des theses partout dans le loan, distrbute and sell theses monde, a des fins commerciales ou autres, sur worldwide, for commercial or non­ support microforme, papier, electronique et/ou commercial purposes, in microform, autres formats. paper, electronic and/or any other formats. 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Canada Acknowledgem ents This thesis could not have been accomplished without the help and support of my research advisor Professor Ralph Mason. His advice and guidance during the past several years was essential in completing this thesis. Ralph has been a good friend throughout this long and arduous process. For that, I am very thankful. I would like to thank the examination committee members Dr. Florinel Balteanu of Skyworks Solutions, Professor Emad Gad, University of Ottawa, Professor Halim Yanikomeroglu, Depart­ ment of Systems and Computer Engineering, Professor Calvin Plett, Department of Electronics and Professor Maitham Shams, Department of Electronics. Their time and comments are greatly appreciated. I would also like to thank Yasser Soliman for technical support with various Cadence and Latex issues. Your help spared me a lot of frustration and ultimately saved me much time. Scholarships from the National Science and Engineering Research Council, Carleton University and Dept, of Electronics are gratefully acknowledged. Without the financial assistance I could not of returned to graduate school. In addition, I would like to thank the Canadian Microelectronics Corporation for their fabrication services and test equipment support. Finally, a big thank you to my family Sandra, Maxwell and Alexander who were wondering if this day would ever come. A bstract A digital input Class D audio amplifier is investigated in this thesis. The intended application is headphone enabled portable audio players such as smart phones and tablets. The topology is intended to be predominately digital and thereby allow for rapid scaling in deep submicron CMOS processes. Class D was chosen for its natural compatibility with pulse modulation schemes and theoretical 100% efficiency. Current Class AB amplifiers offer very good audio quality but generally poor efficiency. The Class D amplifier with global feedback was prototyped with a Field Programmable Gate Array (FPGA) and commercial 16b Analog to Digital converter (ADC). Measurement and sim­ ulation results indicate stable operation with greater than 30 dB of noise rejection at 1 kHz. A revised design operating at a lower frequency with improved noise rejection was simulated. An integral component of the topology is the 2.82 Msps 16b ADC. To meet the power specification of <5 mW a unique variant of the successive approximation algorithm termed the Configurable Offset with Preamplifier (COP) ADC was developed. The core of the ADC consists of a pream­ plifier array and latched comparator. Intentional mismatches are introduced to produce voltage references for the conversion process and thereby eliminating the need for a Digital to Analog Converter (DAC). The core circuits of the COP ADC were implemented in 0.13/xm CMOS. The COP ADC required external digital control and clocks via a FPGA. A passive charge sharing sample and hold circuit and calibration algorithm are also required for a complete solution. Both AC and DC automated measurements yield 13.8b resolution over a 293 mVpp operating range and 6.25 MHz comparator clock. The maximum INL=0.5 LSB, DNL=1 LSB and core power consumption of 1.5 mW. In addition, gain and rejection ratio formulas for a asymmetric differential pair amplifier were derived and correlated well with simulation results. Table of Contents Acknowledgements ii Abstract iii Table of Contents iv List of Tables viii List of Figures ix List of Abbreviations and Symbols xiii 1 Introduction 1 1.1 Motivation ................................................................................................................................. 2 1.2 Objectives.................................................................................................................................... 3 1.3 Contributions.............................................................................................................................. 3 1.4 Organization.............................................................................................................................. 5 2 Background 6 2.1 Digital Audio Source................................................................................................................. 7 2.2 Modulator.................................................................................................................................... 7 2.2.1 Pulse Width Modulation............................................................................................ 8 2.2.2 Sigma-Delta Modulation............................................................................................ 12 2.3 Digital to Analog Converter................................................................................................... 14 2.4 Power Amplifier........................................................................................................................... 14 2.4.1 Linear Amplifiers......................................................................................................... 14 2.4.2 Switching Mode Power Amplifiers .......................................................................... 16 2.5 Speakers........................................................................................................................................ 17 2.6 Power Amplifier Efficiency....................................................................................................... 19 2.6.1 Definitions ................................................................................................................... 19 2.6.2 Linear Power Amplifier Efficiency............................................................................. 20 2.6.3 Class-D Efficiency...................................................................................................... 23 2.7 Key Points ................................................................................................................................. 29 iv 3 Audio Amplifier Technology Review 31 3.1 System Specifications.....................................................................................................................31 3.2 Sources of Distortion................................................................................................................. 33 3.3 Linearization Techniques.......................................................................................................... 34 3.3.1 Negative Feedback....................................................................................................... 35 3.3.2 Alternative Linearization Techniques............................................................................38 3.4 Switching Mode Audio Amplifiers.......................................................................................... 39 3.4.1 Switching Mode Power Amplifier Categories...............................................................40 Category I ................................................................................................................... 40 Category I I ................................................................................................................... 42 Category III ................................................................................................................ 45 Category IV ................................................................................................................... 46 Category V ................................................................................................................... 47 3.4.2 Commercial Class-D Amplifiers................................................................................. 48 3.5 Key Points ................................................................................................................................. 49 4 System Design 50 4.1 System Architecture................................................................................................................. 50 4.1.1 Interpolation Filters.................................................................................................... 53 4.1.2 D PW M ........................................................................................................................... 54 Sigma Delta Modulation............................................................................................ 54 Modulation Index ...................................................................................................... 57 MASH 1-2 Simulations................................................................................................ 57 PW M ............................................................................................................................. 60 Multi-bit Selection C riteria...................................................................................... 60 4.2 Control Loop Analysis.............................................................................................................. 61 4.2.1 Continuous to Discrete T im e..................................................................................... 63 4.3 System Prototype........................................................................................................................ 64 4.3.1 Bode Plot Analysis....................................................................................................... 66 4.3.2 ADC.................................................................................................................................. 68 4.3.3 Simulations..................................................................................................................... 68 4.3.4 Measurements .............................................................................................................. 68 4.4 Revised System Design.............................................................................................................. 71 4.4.1 Interpolation Filters.................................................................................................... 72 4.4.2 PID Compensator........................................................................................................ 73 4.4.3 Simulations..................................................................................................................... 75 4.5 CMOS Class D ..............................................................................................................................80 4.5.1 Switching losses..................................................................................................................80 4.5.2 Conduction losses ............................................................................................................82 4.5.3 Total losses.........................................................................................................................83 4.6 Key Points ................................................................................................................................. 84 v 5 Low Power ADC Design 85 5.1 SAR Algorithm........................................................................................................................ 85 5.2 COP ADC Architecture........................................................................................................ 89 5.2.1 Track-and-Hold.................................................................................................................91 5.2.2 Preamplifier.................................................................................................................... 91 Gain and Rejection Ratios.......................................................................................... 92 Offset Voltage................................................................................................................ 96 Noise ............................................................................................................................. 97 Preamplifier Array Analysis and Simulations...................................................... 98 5.2.3 Comparator......................................................................................................................102 Latched Comparator.....................................................................................................104 Offset Configuration.....................................................................................................106 Comparator N oise........................................................................................................110 5.3 Cascaded Performance..............................................................................................................Ill 5.3.1 Tuning Range...................................................................................................................Ill 5.3.2 Cascaded Noise...............................................................................................................112 5.4 Key Points .................................................................................................................................115 6 ADC Test and Measurements 117 6.1 Integrated Circuit Overview....................................................................................................117 6.2 Digital Interface .......................................................................................................................117 6.3 Measurement System.................................................................................................................121 6.3.1 Printed Circuit B oard..................................................................................................121 6.3.2 Automated Testing.........................................................................................................122 DC Measurements........................................................................................................122 AC Measurements........................................................................................................123 6.4 Measurement Results.................................................................................................................124 6.4.1 DC Measurements.........................................................................................................124 Hysteresis........................................................................................................................125 6.4.2 AC Measurements.........................................................................................................128 Noise ...............................................................................................................................131 6.5 Comparison Table ....................................................................................................................135 6.5.1 Quiescent Power Estimate............................................................................................135 6.5.2 Maximum System Efficiency.........................................................................................137 6.5.3 Other Parameters .........................................................................................................137 6.6 Key Points .................................................................................................................................137 7 Conclusions 139 7.1 Future Work ..............................................................................................................................140 Appendix A Mismatch in differential amplifiers 142 Appendices 142 vi Appendix B PCB CAD Bibliography List of Tables 2.1 Conduction angles and efficiency ratings for linear mode amplifiers.............................. 15 3.1 Low power digital audio system specifications..................................................................... 32 3.2 Overview of current switching mode audio power amplifier techniques.............................40 5.1 Initial COP ADC target specifications................................................................................... 91 5.2 Preamplifier array device parameters(Vcc=1.2V, R=75012 and Ibias=L25mA). . . . 99 5.3 Latched comparator device sizes................................................................................................104 5.4 Comparator mismatched device sizes........................................................................................108 6.1 Pinout with description................................................................................................................119 6.2 Config register settings for programmable offsets..................................................................120 6.3 DC Measured input referred offset resolution and tuning range........................................125 6.4 Measured input referred offset resolution and tuning range...............................................131 6.5 Noise measurements......................................................................................................................133 6.6 Published specifications for digital input Class D audio amplifiers. All power spec­ ifications are for single channel mono operation...................................................................136 List of Figures 2.1 Digital audio system block diagram....................................................................................... 6 2.2 Natural sampling PWM (NPWM) circuit............................................................................ 8 2.3 PWM waveforms for the natural sampling (NPWM) and uniform sampling (UPWM) processes........................................................................................................................................ 9 2.4 Second and third order harmonic distortion relative to fundamental with M=l. . . 11 2.5 Direct digital conversion PCM to PW M ............................................................................ 12 2.6 First order Sigma-Delta modulator: a) System block diagram, b) Input and output time domain waveforms, c) Noise shaped spectral output....................................................13 2.7 Basic circuit configuration of a single ended Class A, AB, B or C amplifier...................15 2.8 Current-Voltage plane operating locus of different power amplifier classes......................16 2.9 Headphone impedance measurement of Sony MDR-E8181.............................................. 18 2.10 Speaker connection configurations, a) single ended, b) differential or BTL.....................18 2.11 Maximum theoretical collector efficiency r?c versus conduction angle................................20 2.12 Normalized maximum power output capability versus conduction angle.........................21 2.13 Collector efficiency r)c of ideal Class-A, B, G2 (a=0.5) amplifiers......................................22 2.14 Average efficiency for Class B, G2 (two level) and G3 (three level) for audio signals with Gaussian probability distribution function [1]........................................................... 23 2.15 Class D circuit: (a) MOS circuit schematic, (b) equivalent ideal circuit..........................24 2.16 Voltage and current waveforms in an ideal Class D switching mode amplifier a) voltage V at the input to the load network, b) resistor voltage vQ, c) Q\ drain 2 current ii, d) Q2 drain current *2, e) resistor current i0.......................................................26 2.17 Switching amplifier with various load networks......................................................................27 2.18 Switching mode amplifier efficiency calculation for various load networks. Resonant frequency 1 MHz, R=16 fi, L=1 mH and C=25.3 nF...........................................................29 ix